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Nearly Optimal Register Allocation with PBQP [chapter]

Lang Hames, Bernhard Scholz
2006 Lecture Notes in Computer Science  
Using an optimal solver for PBQP we were able to solve 97.4% of the register allocation problems in SPEC2000 optimally.  ...  We also present a new solver for PBQP which is based on branch-and-bound and is able to solve register allocations optimally.  ...  With the given framework there is still the algorithmic challenge to solve every register allocation problem in SPEC2000 optimally.  ... 
doi:10.1007/11860990_21 fatcat:dszjqevxabcmnjtbuuu2ddfhbi

SSA-Based Register Allocation with PBQP [chapter]

Sebastian Buchwald, Andreas Zwinkau, Thomas Bersch
2011 Lecture Notes in Computer Science  
Recent research shows that maintaining SSA form allows to split register allocation into separate phases: spilling, register assignment and copy coalescing.  ...  In this paper we present an assignment approach with integrated copy coalescing, which maps the problem to the Partitioned Boolean Quadratic Problem (PBQP).  ...  Conclusion This work combines SSA-based with PBQP-based register allocation and integrates copy coalescing into the assignment process.  ... 
doi:10.1007/978-3-642-19861-8_4 fatcat:6quglcpjy5ec5jyidyubjonca4

Graph Coloring vs. Optimal Register Allocation for Optimizing Compilers [chapter]

Ulrich Hirnschrott, Andreas Krall, Bernhard Scholz
2003 Lecture Notes in Computer Science  
In order to fully exploit the potential of processors, nearly optimal register allocation is of paramount importance.  ...  These irregularities makes the task of register allocation for optimizing compilers more difficult than for regular architectures and register files.  ...  Optimal Register Allocation Optimal register allocation delivers the most accurate register allocation.  ... 
doi:10.1007/978-3-540-45213-3_26 fatcat:essugq7j2fekdg3vxuzjgrq224

RL4ReAl: Reinforcement Learning for Register Allocation [article]

S. VenkataKeerthy, Siddharth Jain, Rohit Aggarwal, Albert Cohen, Ramakrishna Upadrasta
2022 arXiv   pre-print
Experimental results match or outperform the LLVM register allocators, targeting Intel x86 and ARM AArch64.  ...  We propose a novel solution for the Register Allocation problem, leveraging multi-agent hierarchical Reinforcement Learning.  ...  We plan to address other sub-tasks of register allocation: coalescing, multi-allocation and register packing. We will open-source the framework in the near future.  ... 
arXiv:2204.02013v1 fatcat:js7g5rx5czeybnyumfqtw36kli

Code Instruction Selection Based on SSA-Graphs [chapter]

Erik Eckstein, Oliver König, Bernhard Scholz
2003 Lecture Notes in Computer Science  
Patterns defined as graph grammar guide the instruction selection to find (nearly) optimal results.  ...  We present an approach which maps the pattern matching problem to a partitioned boolean quadratic optimization problem (PBQP).  ...  Register allocation assigns hardware registers to pseudo registers.  ... 
doi:10.1007/978-3-540-39920-9_5 fatcat:75wv52iqojh2bkqquw26n5v7yi

Generalized instruction selection usingSSA-graphs

Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec
2008 SIGPLAN notices  
(PBQP ) for finding an optimal instruction selection.  ...  All of the test programs could be compiled within less than half a minute using a heuristic PBQP solver that solves 99.83% of all instances optimally.  ...  Only a single benchmark (consumer-lame) shows a slowdown by 5% that is caused by spill code due to an inferior register allocation. All results have been obtained with the heuristic PBQP solver.  ... 
doi:10.1145/1379023.1375663 fatcat:uj4nqon4lndenowmsrmb7fcwye

Generalized instruction selection usingSSA-graphs

Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec
2008 Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '08  
(PBQP ) for finding an optimal instruction selection.  ...  All of the test programs could be compiled within less than half a minute using a heuristic PBQP solver that solves 99.83% of all instances optimally.  ...  Only a single benchmark (consumer-lame) shows a slowdown by 5% that is caused by spill code due to an inferior register allocation. All results have been obtained with the heuristic PBQP solver.  ... 
doi:10.1145/1375657.1375663 dblp:conf/lctrts/EbnerBSKWK08 fatcat:m5e2gsn745gxxgzn7hwof2emqi

Survey on Combinatorial Register Allocation and Instruction Scheduling [article]

Roberto Castañeda Lozano, Christian Schulte
2019 arXiv   pre-print
This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that  ...  Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating  ...  Section 3.5 closes with a summary of developments and challenges in combinatorial register allocation. Basic Approaches Optimal Register Allocation.  ... 
arXiv:1409.7628v3 fatcat:ebbnooyzgbdvnaaqvtzpth7igi

Survey on Combinatorial Register Allocation and Instruction Scheduling

Roberto Castañeda Lozano, Christian Schulte
2019 ACM Computing Surveys  
This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that  ...  Sweden CHRISTIAN SCHULTE, KTH Royal Institute of Technology, Sweden and RISE SICS, Sweden Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering  ...  Section 3.5 closes with a summary of developments and challenges in combinatorial register allocation. Basic Approaches Optimal Register Allocation.  ... 
doi:10.1145/3200920 fatcat:kb7z453cmjhbzjdxev6qmitqee

Instruction selection by graph transformation

Sebastian Buchwald, Andreas Zwinkau
2010 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems - CASES '10  
We confirm the capabilities of PBQP-based instruction selection by a comparison with a finely-tuned hand-written instruction selection.  ...  Currently, the only approach allowing us to pair graphbased instruction selection with linear time complexity is the mapping to the Partitioned Boolean Quadratic Problem (PBQP).  ...  RELATED WORK The PBQP was first used for register allocation [17, 29] and is often [20, 25, 31] classified with approaches like integer linear programming, since it can be used to find an optimal solution  ... 
doi:10.1145/1878921.1878926 dblp:conf/cases/BuchwaldZ10 fatcat:fa5ngnxcyffxff47avsy7njx4i

Optimal Register Allocation in Polynomial Time [chapter]

Philipp Klaus Krause
2013 Lecture Notes in Computer Science  
The assignment of registers is optimal with respect to spill and rematerialization costs, register preferences and coalescing.  ...  A graph-coloring register allocator that optimally allocates registers for structured programs in polynomial time is presented. It can handle register aliasing.  ...  There are also approaches modeling register allocation as a partitioned boolean quadratic programming (PBQP) problem [31, 23] .  ... 
doi:10.1007/978-3-642-37051-9_1 fatcat:56uuf76ys5dqtoepojz7lo4rxa

Effective compiler generation by architecture description

Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner
2006 SIGPLAN notices  
From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler.  ...  A µ-instruction of an addition ing register allocator and an optimal allocator based on partitioned boolean quadratic programming (PBQP) are included [HKS03] .  ...  The register model is the input both for the graph coloring and the PBQP based register allocator and it is used in all calculations of data dependency.  ... 
doi:10.1145/1159974.1134671 fatcat:yanz6oia2fhdtm25l32fokvuba

Effective compiler generation by architecture description

Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner
2006 Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers and tool support for embedded systems - LCTES '06  
From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler.  ...  A µ-instruction of an addition ing register allocator and an optimal allocator based on partitioned boolean quadratic programming (PBQP) are included [HKS03] .  ...  The register model is the input both for the graph coloring and the PBQP based register allocator and it is used in all calculations of data dependency.  ... 
doi:10.1145/1134650.1134671 dblp:conf/lctrts/FarfelederKSB06 fatcat:a57pdprmkbeozk4jfmwzbxll4q

Combinatorial Register Allocation and Instruction Scheduling [article]

Roberto Castañeda Lozano, Mats Carlsson, Gabriel Hjort Blindell, and Christian Schulte
2019 arXiv   pre-print
This paper introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems.  ...  Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches.  ...  IP is the most widely used optimization technique with the exception of Scholz and Eckstein [85] using PBQP, Bashford and Leupers [9] using CP, and Kessler and Bednarski [56] using DP.  ... 
arXiv:1804.02452v5 fatcat:573hngx2ijfv7k6sl42o4aht7m

Trace register allocation

Josef Eisl
2015 Companion Proceedings of the 2015 ACM SIGPLAN International Conference on Systems, Programming, Languages and Applications: Software for Humanity - SPLASH Companion 2015  
We developed a novel trace register allocation framework, which competes with global approaches in both, compile time and code quality.  ...  Furthermore, to demonstrate the flexibility of trace register allocation, we seamlessly reduce register allocation time in a range from 0 to 40%, depending on how much peak performance penalty we are willing  ...  To overcome this issue, they developed a heuristic PBQP solver that exhibits nearly linear run time.  ... 
doi:10.1145/2814189.2814199 dblp:conf/oopsla/Eisl15 fatcat:nmkxq2jezfbfbpkz2kknx7rzl4
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