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Nanoelectromechanical contact switches

Owen Y. Loh, Horacio D. Espinosa
2012 Nature Nanotechnology  
Nanoelectromechanical (NEM) switch technologies are being investigated because they offer reduced leakage currents 1-3 -which leads to reduced power consumption and improved ON/OFF ratios 4,5 .  ...  devices -and also by hybrid NEM-CMOS devices 6 -is highly advantageous.  ...  Improvement in hold (> 2) and read (> 3) static noise margins Allows maintained cell stability with continued scaling (difficult to maintain stability while scaling conventional six-transistor CMOS-SRAM  ... 
doi:10.1038/nnano.2012.40 pmid:22543427 fatcat:b6q3asz7kzfzdf76wqdpg46wei

Nanoelectromechanical Switches for Low-Power Digital Computing

Alexis Peschot, Chuang Qian, Tsu-Jae Liu
2015 Micromachines  
applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh  ...  Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic  ...  For example, a hybrid NEMS/CMOS static random-access memory (SRAM) cell design for lower static power dissipation and improved cell stability is proposed in [48] , and projected to provide a reduction  ... 
doi:10.3390/mi6081046 fatcat:qjkns2w3iffdnnpyzudgpzm7ue

Design Issues for NEM-Relay-Based SRAM Devices

Sebastià A. Bota, Jaume Verd, Xavier Gili, Joan Barceló, Gabriel Torrens, Rafel Perelló, Tomeu Alorda, Carol de Benito, Jaume Segura, N. Mastorakis, V. Mladenov, A. Bulucea
2018 MATEC Web of Conferences  
Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays.  ...  We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays.  ...  This work has been supported by the Spanish Ministry of Economy and Competitiveness (Project TEC2014-52878-R).  ... 
doi:10.1051/matecconf/201821001005 fatcat:isvfdvlvsvcprhrcudqu7zvstu

Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

Katherine Boucart
2010
Kim et al. at the University of Michigan developed an SRAM cell based on heterojunction Tunnel FETs that showed greatly reduced leakage in comparison with conventional CMOS [77].  ...  These dual-V T circuits use low-V T CMOS on the critical paths, where speed is critical but leakage will be high, and high-V T CMOS off the critical paths where leakage can be reduced without sacrificing  ...  Studied the micro-architecture, logic, and schematics in order to target untested paths. Excluded untestable faults. Achieved the project goal of 98% coverage for the multiplier. KATHY BOUCART  ... 
doi:10.5075/epfl-thesis-4729 fatcat:y3qrxtxffbd7tfthofrrewkxua

Instrumentation development to study candidate materials for an organic piezoelectronic transistor [article]

Sergejs Afanasjevs, University Of Edinburgh, Konstantin Kamenev, Vasileios Koutsos
2021
This, in turn, implies small driving voltages, higher processing speeds and denser integration/scaling capabilities.  ...  ambient and 3 gigapascals (GPa) (pressure within the suitable range for OPET application).  ...  Konstantin Kamenev, for his guidance, support and patience. Not only he offered me the funded PhD but also opened my eyes to the beautiful world of HP science and its small details.  ... 
doi:10.7488/era/1500 fatcat:wbj3dz5i6jhjvlcpsgtlq7u7p4