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NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity
2015
Integration
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We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. ...
on processors built with FinFET for endurable operations. ...
In this work, we focus on the NBTI reliability issue of a modern GPU made of FinFET and propose to address this problem by exploiting the device heterogeneity. ...
doi:10.1016/j.vlsi.2015.04.003
fatcat:gcpiyjro2rfhjbuuv5pkyytqiu
A Survey of Architectural Techniques for Managing Process Variation
2016
ACM Computing Surveys
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We also classify these techniques based on several important parameters to bring out their similarities and differences. ...
The reduced utilization of ports with longer access time helps in reducing NBTI degradation on them. Thus, this technique shifts more NBTI degradation to ports which are less affected by PV. ...
CPU-GPU heterogeneous systems will be absolutely vital and yet challenging. ...
doi:10.1145/2871167
fatcat:6isx7an56ze63jqnpbkuw5pdcm
Performance Variation in Digital Systems:Workload Dependent Modeling and Mitigation
[article]
2021
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We focus on a finFET-based SRAM cell at 10 nm nodes described by PTM modelcards [50] . ...
We focus on a finFET-based SRAM cell at 10 nm nodes described by PTM modelcards [50] . ...
Other metrics focus on the quality of the semiconductor fabrication process. ...
doi:10.26240/heal.ntua.21941
fatcat:6i5vt2rk3jaabdxtublpupx43y
Reliable Software for Unreliable Hardware - A Cross-Layer Approach
2015
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In the cross-layer optimization flow, these reliability models are leveraged by different techniques at different system levels to quantify the reliability-wise importance of different ...
models to quantify three key important reliability aspects at the instruction granularity, i.e. (1) Instruction vulnerability Index (IVI) that estimates the instruction's vulnerability to soft errors by ...
It is shown that the FinFET devices have low susceptibility to soft errors compared to the planar CMOS devices, for instance, SRAMs using FinFETs at 22nm yield an approximately 3.5x reduction in the SER ...
doi:10.5445/ir/1000049847
fatcat:oidka5lbj5eqfh273z3r3vskgi