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Multiway VLSI circuit partitioning based on dual net representation

J. Cong, W. Juan Labio, N. Shivakumar
1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
for multi-way circuit partitioning based on dual net transformation.  ...  In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm  ...  Acknowledgments The authors would like to thank Phil Kuekes and Greg Snider at Hewlett-Packard Laboratory for providing benchmark circuits.  ... 
doi:10.1109/43.494703 fatcat:mvlckfqmorgnfnn6xzpvqa4xqq

Comparative Study Of Ant Colony And Genetic Algorithms For Vlsi Circuit Partitioning

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel
2009 Zenodo  
Results obtained show that Genetic algorithms out perform Ant Colony optimization technique when tested on the VLSI circuit bi-partitioning problem.  ...  This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-partitioning.  ...  RESULTS AND DISCUSSION The performance of the ACO and GA algorithms in tested on circuit partitioning instances (net lists) given on the MARCO GSRC VLSI CAD Bookshelf website [30] .  ... 
doi:10.5281/zenodo.1082181 fatcat:enswqwarcvbrfasm6x2qysrbi4

Genetic Algorithm Based Approach To Circuit Partitioning

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel
2010 International Journal of Computer and Electrical Engineering  
In this paper multiway circuit partitioning of circuits using Genetic Algorithms has been attempted.  ...  Results obtained show the versatility of the proposed method in solving NP hard problems like circuit partitioning.  ...  How ever, to compare the results with already available results, the method has been tried on circuit partitioning instances (net lists) available on MARCO GSRC VLSI CAD Bookshelf website.  ... 
doi:10.7763/ijcee.2010.v2.136 fatcat:vr5blsoq4jewdgp2lf6mappzyy

Partitioning Hypergraphs in Scientific Computing Applications through Vertex Separators on Graphs

Enver Kayaaslan, Ali Pinar, Ümit Çatalyürek, Cevdet Aykanat
2012 SIAM Journal on Scientific Computing  
Specifically, we investigate how to solve the hypergraph partitioning problem by seeking a vertex separator on its net intersection graph (NIG), where each net of the hypergraph is represented by a vertex  ...  This work addresses one method for this trade-off by solving the hypergraph partitioning problem by finding vertex separators on graphs.  ...  Other circuit representation models were also proposed and used in the VLSI literature including dual hypergraph, cliquenet graph (CNG), and NIG [2] .  ... 
doi:10.1137/100810022 fatcat:7hmfwrmdgrgypdusqkh42v7rti

Combinatorial Optimization In Vlsi Hypergraph Partitioning Using Taguchi Methods

P.Subbaraj, S.Saravanasankar, S.Anand
2010 Zenodo  
This work addresses the methods to solve Very Large Scale Integration (VLSI) circuit partitioning problem with dual objectives, viz., 1.  ...  Minimizing the number of interconnection between partitions, that is, the cut size of the circuit and 2. Balancing the area occupied by the partitions.  ...  Proposed methodology A GA based heuristic namely Hybrid Taguchi Genetic Algorithm (HTGA) is proposed in this work, to solve the VLSI circuit partitioning problem with dual objectives of minimizing the  ... 
doi:10.5281/zenodo.823861 fatcat:suvw37q6cjey7pt6kwvvqwv57a

Hypergraph Partitioning through Vertex Separators on Graphs [article]

Enver Kayaaslan, Ali Pinar, Umit V. Catalyurek, Cevdet Aykanat
2011 arXiv   pre-print
Specifically, we investigate how to solve the hypergraph partitioning problem by seeking a vertex separator on its net intersection graph (NIG), where each net of the hypergraph is represented by a vertex  ...  This work addresses one method for this trade-off by solving the hypergraph partitioning problem by finding vertex separators on graphs.  ...  Other circuit representation models were also proposed and used in the VLSI literature including dual hypergraph, cliquenet graph (CNG) and net-intersection graph (NIG) [2] .  ... 
arXiv:1103.0106v1 fatcat:i76667zblzemxblfny5xbyp26i

Tutorial on VLSI Partitioning

Sao-Jie Chen, Chung-Kuan Cheng
2000 VLSI design (Print)  
The tutorial introduces the partitioning with applications to VLSI circuit designs.  ...  We depict the models of multiple pin nets for the partitioning processes.  ...  with applications to VLSI circuit designs.  ... 
doi:10.1155/2000/53913 fatcat:rjeorq3akjcbneo5mjdzbz4ywy

Decomposing linear programs for parallel solution [chapter]

Ali Pinar, Ümit V. Çatalyürek, Cevdet Aykanat, Mustafa Pinar
1996 Lecture Notes in Computer Science  
A Kernighan-Lin based multiway h ypergraph partitioning heuristic is implemented for experimenting with the performance of the proposed hypergraph models on the decomposition of the LP problems selected  ...  In these models, the decomposition problem reduces to the well-known hypergraph partitioning problem.  ...  Sanchis's algorithm (SN) is used for multiway partitioning of hypergraph representations of the constraint matrices.  ... 
doi:10.1007/3-540-60902-4_50 fatcat:ofxvs7o6yjduzdnprvtgjh4gzu

New spectral methods for ratio cut partitioning and clustering

L. Hagen, A.B. Kahng
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Finally, we discuss the very natural intersection graph representation of the circuit netlist as a basis for partitioning, and propose a heuristic based on spectral ratio cut partitioning of the netlist  ...  Partitioning of circuit netlists is important in many phases of VLSI design, ranging from layout to testing and hardware simulation.  ...  become reasonable tasks on VLSI CAD workstation platforms.  ... 
doi:10.1109/43.159993 fatcat:jostndvucnb4phxnuwucmf2wty

Multilevel circuit partitioning

C.J. Alpert, Jen-Hsin Huang, A.B. Kahng
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Our method also uses a new technique to control the number of levels in our matching-based clustering algorithm.  ...  Further, our algorithm generates solutions better than the best known mincut bipartitionings for seven of the ACM/SIGDA benchmark circuits, including golem3 (which has over 100 000 cells).  ...  [44] proposed an extension of Sanchis' multiway partitioning algorithm that alternates "primal" passes of module moves with "dual" passes of net moves; however, run times for dual passes are a factor  ... 
doi:10.1109/43.712098 fatcat:nojkvivlu5dsvjm7z4lhllkqle

Multilevel circuit partitioning

Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
Our method also uses a new technique to control the number of levels in our matching-based clustering algorithm.  ...  Further, our algorithm generates solutions better than the best known mincut bipartitionings for seven of the ACM/SIGDA benchmark circuits, including golem3 (which has over 100 000 cells).  ...  [44] proposed an extension of Sanchis' multiway partitioning algorithm that alternates "primal" passes of module moves with "dual" passes of net moves; however, run times for dual passes are a factor  ... 
doi:10.1145/266021.266275 dblp:conf/dac/AlpertHK97 fatcat:xy6chkc3m5bo5kjywsxqqqnw24

Permuting Sparse Rectangular Matrices into Block-Diagonal Form

Cevdet Aykanat, Ali Pinar, Ümit V. Çatalyürek
2004 SIAM Journal on Scientific Computing  
Our experiments on a wide range of matrices, using state-of-theart graph and hypergraph partitioning tools MeTiS and PaToH, revealed that the proposed methods yield very e ective solutions both in terms  ...  and propose new ones, and nally present a thorough empirical study of these techniques.  ...  In Section 7.1, we brie y discuss alternative circuit representation models proposed by the VLSI community for circuit partitioning and placement.  ... 
doi:10.1137/s1064827502401953 fatcat:jeqct56t4jdm5bvmye4xkakv6i

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis

Sheldon X.-D. Tan, C.-J.Richard Shi
2003 Integration  
This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs).  ...  The proposed algorithm has been implemented and applied to symbolic analysis of several practical analog integrated circuits.  ...  Acknowledgements The authors thank three reviewers for their valuable and constructive comments of this work that improve the representation of this paper.  ... 
doi:10.1016/s0167-9260(03)00002-6 fatcat:5k7l7xscdrei3dp4qhun7rt3au

Recent directions in netlist partitioning: a survey

Charles J Alpert, Andrew B Kahng
1995 Integration  
Algorithms based on geometric representations embed the circuit netlist in some type of geometry", e.g, a 1-dimensional linear ordering or a multi-dimensional vector space; the embeddings are commonly  ...  ., two-phase partitioning. The paper concludes with a discussion of benchmarking in the VLSI CAD partitioning literature and some perspectives on more promising directions for future work.  ...  Figure 1 : Representations of a circuit with 7 modules and 10 signal nets: a circuit diagram with all inputs on the left side of the modules and all outputs on the right side; b the hypergraph representation  ... 
doi:10.1016/0167-9260(95)00008-4 fatcat:337iiybf3vhuzlybuub3wlvfiy

Fundamental CAD algorithms

M.A. Breuer, M. Sarrafzadeh, F. Somenzi
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we focus on several of the fundamental CAD abstractions, models, concepts and algorithms that have had a significant impact on this field.  ...  VLSI CAD is a dynamic area where problem definitions are continually changing due to complexity, technology and design methodology.  ...  A match may span a choice gate, but can use only one of its inputs. The combined representation of multiple decompositions based on choice gates is called mapping graph.  ... 
doi:10.1109/43.898826 fatcat:jwvmbqh4nrbzloxpiacb7j2pse
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