Filters








11,481 Hits in 2.4 sec

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

Ahmed K. Abousamra, Alex K. Jones, Rami G. Melhem
2011 Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers - HiPEAC '11  
Multithreaded applications generally exhibit sharing of data among the program threads, which generates coherence and data traffic on the NoC.  ...  co-designed system which also exploits communication locality in multithreaded applications.  ...  Finally, using simulation, we study the effects of the different design choices and demonstrate the merits and scalability of our NoC-aware cache design.  ... 
doi:10.1145/1944862.1944891 dblp:conf/hipeac/AbousamraJM11 fatcat:wm4jejvzcbhcdnefbg3ibu2og4

Reconfigurable Multithreading Architectures: A Survey [chapter]

Pavel G. Zaykov, Georgi K. Kuzmanov, Georgi N. Gaydadjiev
2009 Lecture Notes in Computer Science  
This paper provides a survey on the existing proposals in the field of reconfigurable multithreading (ρMT) architectures.  ...  More specifically, we identify reconfigurable architectures that provide implicit, explicit or no architectural support for ρMT.  ...  Acknowledgments This work was supported by the HiPEAC European Network of Excellencecluster 1200 (FP6-Contract number IST-004408) and by the Dutch Technology Foundation STW, applied science division of  ... 
doi:10.1007/978-3-642-03138-0_29 fatcat:bhxqyiqrqjg3tbuyt2yvnvhx2y

Programming Abstractions and Toolchain for Dataflow Multithreading Architectures

Kyriakos Stavrou, Demos Pavlou, Marios Nikolaides, Panayiotis Petrides, Paraskevas Evripidou, Pedro Trancoso, Zdravko Popovic, Roberto Giorgi
2009 2009 Eighth International Symposium on Parallel and Distributed Computing  
In this work we propose an abstraction layer that enables compiling and running a program written for an abstract Dataflow Multithreading architecture on different implementations.  ...  In particular, the Dataflow Multithreading architectures have proven to be good candidates for these systems.  ...  Acknowledgments This project was partially funded by HiPEAC (EU FP6 IST 004408, FP7 IST 217068), SARC (EU FP6 FET 27648) and the Cyprus Research Promotion Foundation under the grant ΔΠE/0505/25.  ... 
doi:10.1109/ispdc.2009.35 dblp:conf/ispdc/StavrouPNPETPG09 fatcat:hj24bpcpxfag7a5ikk6uh2oygu

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  We also thank Jennifer Anderson of DEC Western Research Laboratory for copies of the SpecFP95 benchmarks, parallelized by the most recent version of the SUIF compiler, and Sujay Parekh for comments on  ...  Our future work includes compiler and operating systems support for optimizing programs targeted for SMT and combining SMT's multithreading capability with multiprocessing architectures.  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam

An Initial Evaluation of the Tera Multithreaded Architecture and Programming System Using the C3I Parallel Benchmark Suite

S. Brunett, J. Thornley, M. Ellenbecker
1998 Proceedings of the IEEE/ACM SC98 Conference  
The Tera Multithreaded Architecture (MTA) is a radical new architecture intended to revolutionize high-performance computing in both the scientific and commercial marketplaces.  ...  In this paper, we attempt to provide an objective initial evaluation of the performance of the Tera multithreaded architecture and programming system for general-purpose applications.  ...  programs and their comments on this paper.  ... 
doi:10.1109/sc.1998.10048 dblp:conf/sc/BrunettTE98 fatcat:p4jooadzhrekza43ksqs2c3iu4

Multithreading decoupled architectures for complexity-effective general purpose computing

Michael Sung, Ronny Krashinsky, Krste Asanović
2001 SIGARCH Computer Architecture News  
A proposal for a multithreaded decoupled control/access/execute architecture is presented as a platform for achieving high performance on general purpose workloads.  ...  It is argued that such a decoupled architecture is more complexity-effective and scalable than comparable superscalar processors, which incorporate enormous amounts of complexity for modest performance  ...  Also, it is possible to allow the compiler more opportunity to decouple a given program by utilizing multithreading compiler techniques.  ... 
doi:10.1145/563647.563658 fatcat:fjmdpove5ravhclvctbfurz6im

Sandbridge Software Tools [chapter]

John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis
2005 Lecture Notes in Computer Science  
Using just-intime compiler technology, we dynamically compile an executing program and processor model to a target platform providing fast interactive responses with accelerated simulation capability.  ...  We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor.  ...  Dynamically compiled multithreaded simulation is more complicated and described in Section III.B.  ... 
doi:10.1007/11512622_29 fatcat:l3sd7vacdfgu3e5fm6g27x2pei

Automatic compiler techniques for thread coarsening for multithreaded architectures

Gary M. Zoppetti, Gagan Agrawal, Lori Pollock, Jose Nelson Amaral, Xinan Tang, Guang Gao
2000 Proceedings of the 14th international conference on Supercomputing - ICS '00  
Thread partitioning is the most important task in compiling high-level languages for multithreaded architectures.  ...  Our experiments were performed using the EARTH-C compiler and the EARTH multithreaded architecture model emulated on both a cluster of Pentium PCs and a distributed memory multiprocessor.  ...  Acknowledgments We would like to thank Laurie Hendren and the ACAPS group at McGill University for providing us with a copy of the EARTH-C compiler.  ... 
doi:10.1145/335231.335261 dblp:conf/ics/ZoppettiAPATG00 fatcat:k3ny2hxqtbdchjczrnxtynivbu

Part I: Special Issue on Parallel Architectures and Compilation Techniques

Jean-Luc Gaudiot
1996 International journal of parallel programming  
Welcome to part one of this special issue on Parallel Architectures and Compilation Techniques.  ...  working at the precise boundary between architecture and compilers for parallel machines.  ...  The results of the experiments point to the viability of the multithreaded model of execution both in terms of latency tolerance for multiprocessor environments and in terms of single processor performance  ... 
doi:10.1007/bf03356748 fatcat:4qjgh46xlvg5vd7tsgxqlele3u

Speculative multithreaded processors

G.S. Sohi, A. Roth
2001 Computer  
With this trend comes a renewed and increasing interest in multithreaded architectures.  ...  Speculative Multithreaded Processors S emiconductor technologies-along with innovative computer architectures-have provided the bricks and mortar for building phenomenal improvements in processing speed  ...  School, and by an Intel Foundation Graduate Fellowship.  ... 
doi:10.1109/2.917542 fatcat:fsdtjvtfsnheljrwckngvqg73m

Implementing a non-strict functional programming language on a threaded architecture [chapter]

Shigeru Kusakabe, Kentaro Inenaga, Makoto Amamiya, Xinan Tang, Andres Marquez, Guang R. Gao
1999 Lecture Notes in Computer Science  
Our compiler generates codes in Threaded-C, which is a lower-level programming language for EARTH. We have developed translation rules, and integrated them into the compiler.  ...  The combination of a language with ne-grain implicit parallelism and a dataow e v aluation scheme is suitable for high-level programming on massively parallel architectures.  ...  However, since our basic execution model is a multithreaded execution model extended from Datarol model, multithreaded architectures which have special support for negrain parallel processing are preferable  ... 
doi:10.1007/bfb0097894 fatcat:kjwlaxfjd5citccnro6auetqga

An elementary processor architecture with simultaneous instruction issuing from multiple threads

Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, Teiji Nishizawa
1992 Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92  
In this paper, we propose a multithreaded processor architecture which improves machine throughput.  ...  In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there  ...  In order to overcome these problems, we introduced two kinds of multithreading techniques into our processor architecture: concurrent multithreading and parallel multithreading.  ... 
doi:10.1145/139669.139710 dblp:conf/isca/HirataKNMNNN92 fatcat:2mtvetydrjberag77rtikjl2xa

An elementary processor architecture with simultaneous instruction issuing from multiple threads

Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, Teiji Nishizawa
1992 SIGARCH Computer Architecture News  
In this paper, we propose a multithreaded processor architecture which improves machine throughput.  ...  In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there  ...  In order to overcome these problems, we introduced two kinds of multithreading techniques into our processor architecture: concurrent multithreading and parallel multithreading.  ... 
doi:10.1145/146628.139710 fatcat:xklw4rswkbczjk63mmwkynn5vi

Speculative Multithreaded Processors [chapter]

Gurindar S. Sohi, Amir Roth
2000 Lecture Notes in Computer Science  
Multithreaded architectures provide new opportunities for extracting parallelism from a single program via thread level speculation.  ...  to support the simultaneous execution of collections of speculative and non-speculative threads.  ...  and by an Intel Foundation Graduate Fellowship.  ... 
doi:10.1007/3-540-44467-x_23 fatcat:2ecvlteawzb57ek3hz57axiejy

Multithreaded Processors

T. Ungerer
2002 Computer journal  
This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.  ...  The execution units are multiplexed between the threads in the register sets.  ...  The Simultaneous Speculation Scheduling (S3) [103, 104, 105, 106] is a combined compiler and architecture technique to control multiple path execution.  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm
« Previous Showing results 1 — 15 out of 11,481 results