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Multitasking and multithreading on a multiprocessor with virtual shared memory

H.L. Muller, P.W.A. Stallard, D.H.D. Warren
Proceedings. Second International Symposium on High-Performance Computer Architecture  
In this paper we investigate the combination of multitasking and multithreading in a (virtual) shared memory parallel machine running a number of parallel applications.  ...  In particular, we investigate whether it is better to run related threads, or unrelated threads on each node to achieve the best system throughput and to complete a mix of applications as quickly as possible  ...  In this paper we investigate the combination of multithreading with multitasking for parallel applications running on parallel machines with a virtual shared y Work supported by ESPRIT OMI/HORN P7249.  ... 
doi:10.1109/hpca.1996.501187 dblp:conf/hpca/MullerSW96 fatcat:avl3lk5yoran7odeoxrq3qajx4

Performance analysis of N-computing device under various load conditions

Snigdha Srivastava
2012 IOSR Journal of Computer Engineering  
We will create a multiuser environment on a uniprocessor system; this can be achieved, when there is a separate kernel for each user in the same operating system.  ...  In other words we want to utilize the full processing power of a personal computer for number of users simultaneously and also provide better performance at less cost.  ...  Distributed user applications that communicate across a network, for example through message passing, virtual shared memory, or object invocation.  ... 
doi:10.9790/0661-0744652 fatcat:klqyxqbvyncpbcm4gh6rui4uvq

Hyper Threading Technology in Hardware Architecture for Processor Efficiency Enhancement

Neha Srivastava, Kalyan Awasthi, And Sadaf Z. Rizvi
2015 SAMRIDDHI A Journal of Physical Sciences Engineering and Technology  
From a micro architecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources.  ...  Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors  ...  The logical processors share most of the processor resources and can increase system performance when concurrently executing multithreaded or multitasked workloads [2] [3] .  ... 
doi:10.18090/samriddhi.v3i1.1611 fatcat:34bvho3tw5fdxmfzfowtwgcqcm

Design principles for a virtual multiprocessor

Philip Machanick
2007 Proceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries - SAICSIT '07  
A multitasking or multithreaded workload will do better on a CMP design; a floating-point application without many decision points will do better on a machine with ILP as its main parallelism.  ...  The result is a virtual multiprocessor (or vMP) which at the software level looks like either a uniprocessor with n clusters of functional units, or an n-core CMP, depending on how the data path is configured  ...  More recently, CMPs (or multicore designs) have moved into the mainstream, with designs from Intel [6] and AMD [2] illustrating that consumer multitasking and multithreaded workloads are a reasonable  ... 
doi:10.1145/1292491.1292500 dblp:conf/saicsit/Machanick07 fatcat:gikire7575cxvboedrlhmmgwgm

A multithreaded PowerPC processor for commercial servers

J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, S. R. Kunkel
2000 IBM Journal of Research and Development  
A multithreaded PowerPC processor for commercial servers This paper describes the microarchitecture of the RS64 IV, a multithreaded PowerPC ® processor, and its memory system.  ...  This provides a significant throughput increase while adding less than 5% to the chip area and having very little impact on cycle time.  ...  Because virtual addresses are shared across all tasks, the TLB and storage-description register 1 (SDR1), which contains the address of the hashed page table, are shared between the threads.  ... 
doi:10.1147/rd.446.0885 fatcat:6n35k2rsqvbpvigzujaizluw5a

A simple power-aware scheduling for multicore systems when running real-time applications

Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, Jose Duato
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
Different scheduling alternatives have been evaluated, and experimental results show that using a fair scheduling policy, the proposed algorithm provides, on average, energy savings ranging from 34% to  ...  ., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational requirements.  ...  We have assumed a sim- Cache memory Disabled Memory access latency ple model where one core working at its lowest speed can guarantees the WCET of one only task running in it with low speed.  ... 
doi:10.1109/ipdps.2008.4536220 dblp:conf/ipps/BautistaSHPD08 fatcat:c5a43zrdifghnjyewfueg4gcci

A single-chip multiprocessor

B.A. Nayfeh, K. Olukotun
1997 Computer  
To make a shared memory multiprocessor, the data caches could be made writethrough, or a MESI (modified, exclusive, shared, and invalid) cache-coherence protocol could be established between the primary  ...  As a result, they perform and utilize area comparably on multithreaded code.  ... 
doi:10.1109/2.612253 fatcat:l645n6krxnaphalnk5w6pogwye

Architectural differences of efficient sequential and parallel computers

Martti J. Forsell
2002 Journal of systems architecture  
and multiprocessor setups.  ...  Thus, designing a computer for efficient sequential computation leads to a very different architecture than designing one for efficient parallel computation and there exists no single optimal architecture  ...  The advantages of multithreading include more flexible multitasking, better toleration of memory latencies, and better possibilities for extensive superpipelining.  ... 
doi:10.1016/s1383-7621(02)00064-4 fatcat:graadduelvdupc72gz6bpwsyxm

Nonrigid image registration in shared-memory multiprocessor environments with application to brains, breasts, and bees

T. Rohlfing, C.R. Maurer
2003 IEEE Transactions on Information Technology in Biomedicine  
It takes advantage of shared-memory multiprocessor computer architectures using multithreaded programming by partitioning of data and partitioning of tasks, depending on the computational subproblem.  ...  The method is demonstrated to perform the computation of intra-operative brain deformation in less than a minute using 64 CPUs on a 128-CPU shared-memory supercomputer (SGI Origin 3800).  ...  Lewis for his generous help and expert advice on thread programming and the reviewers of this paper for their valuable comments and helpful suggestions.  ... 
doi:10.1109/titb.2003.808506 pmid:12670015 fatcat:i6obinr36fd2zniaufe6yahn2y

Synchronization, coherence, and event ordering in multiprocessors

M. Dubois, C. Scheurich, F.A. Briggs
1988 Computer  
The instruction set of a multiprocessor usually contains basic instructions that are used to implement synchronization and communication between cooperating processes.  ...  and operating systems.  ...  In a shared-memory multiprocessor, interprocess communication can be as simple as one processor writing to a particular memory location and another processor reading that memory location.  ... 
doi:10.1109/2.15 fatcat:yflu46ikqjbbdh4tdgalpc5wmm

Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors

Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov
2008 ACM Transactions on Design Automation of Electronic Systems  
Maintaining local caches coherently in shared-memory multiprocessors results in significant power consumption.  ...  providing minimal impact on performance and memory access latency [Martin et al. 2002 [Martin et al. , 2003 ].  ...  SHARED ADDRESS SEGMENTS (SAS) ARCHITECTURE The proposed SAS methodology is applied on platforms with no virtual memory.  ... 
doi:10.1145/1297666.1297682 fatcat:72xf7unyuzcqxjeutbvsb3vwse

Simulation of hybrid computer architectures: simulators, methodologies and recommendations

Pranav, Jaehwan John Lee
2007 2007 IFIP International Conference on Very Large Scale Integration  
Industry trends indicate that such coprocessors will be socket compatible to microprocessors and will be integrated on existing multiprocessor motherboards without any glue logic.  ...  Next we present a survey of existing simulators and simulation methodologies for simulation of components of hybrid computing systems.  ...  It would be beneficial if these RL coprocessors are used as multitasking shared resources.  ... 
doi:10.1109/vlsisoc.2007.4402490 dblp:conf/vlsi/VaidyaL07 fatcat:kzamgosiyndxnec6lhos7pbmru

Multi-core: Adding a New Dimension to Computing [article]

Md. Tanvir Al Amin
2010 arXiv   pre-print
As a result, the microprocessor industry has started exploring the technology along a different dimension.  ...  That quest has suddenly come to a halt due to fundamental bounds applied by physical laws. But, demand for more and more computational power is still prevalent in the computing world.  ...  On the other hand, multicore systems work in shared memory, and in a lot of cases shared cache systems. Processor to processor communication is not expensive as both are in a single package.  ... 
arXiv:1011.3382v1 fatcat:lytsvogjibgkvjr5ty5abtecae

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Manju Khari, Raghvendra Kumar, Dac-Nhuong Le, Jyotir Moy Chatterjee
2017 International Journal of Computer Network and Information Security  
A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system.  ...  In this endeavor, network interfaces mainly differ in the way a network physically connects to a multicore system along with the data path.  ...  Yaser Ahangari Nanehkaran (2013) Chip multiprocessor, Hyper Transport, printed circuit board, front side bus, multithread, DRAM memory, and cache.  ... 
doi:10.5815/ijcnis.2017.11.06 fatcat:vggnrtxxfjah5aimi34ah7l2qq

CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters [chapter]

Peter Jamieson, Angelos Bilas
2001 Lecture Notes in Computer Science  
In this work we address this problem by providing a single cluster image with respect to thread and memory management to programmers.  ...  We implement our system on a 16-processor cluster interconnected with a low-latency, high-bandwidth system area network.  ...  Finally, Paul McHardy and Alexis Armour for their insights on the paper.  ... 
doi:10.1007/3-540-44587-0_15 fatcat:eau3afoxebg2bdubp67bihnogm
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