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Multiprocessor DSP scheduling in system-on-a-chip architectures

P. Gai, L. Abeni, G. Buttazzo
Proceedings 14th Euromicro Conference on Real-Time Systems. Euromicro RTS 2002  
This paper discusses the problem of multiprocessor scheduling for asymmetric architectures composed by a general purpose CPU and a DSP.  ...  A possible solution to cope with embedded applications with high computational requirements is to adopt multiple-processor-on-a-chip architectures.  ...  The problem of DSP scheduling in asymmetric multiprocessor architectures can be viewed as a special case of scheduling with shared resources in multiprocessor distributed systems.  ... 
doi:10.1109/emrts.2002.1019203 dblp:conf/ecrts/GaiAB02 fatcat:lfw7lp57oraafdgmp5zkxzeewu

Software environment for a multiprocessor DSP

Asawaree Kalavade, Joe Othmer, Bryan Ackland, K. J. Singh
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
In this paper, we describe the software environment for Daytona, a single-chip, bus-based, shared-memory, multiprocessor DSP. The software environment is designed around a layered architecture.  ...  Tools at the higher layer focus on improving the programmability of the system and include a run-time kernel and parallelizing tools.  ...  The architecture incorporates a 128-bit wide on-chip split transaction bus (ST bus).  ... 
doi:10.1145/309847.310078 dblp:conf/dac/KalavadeOAS99 fatcat:5o32coryxzeuroxi3x54zct7la

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications

N. Sedaghati-Mokhtari, M. N. Bojnordi, S. M. Fakhraie
2007 Proceedings of the ... International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems  
In this paper, we propose a multiprocessor DSP simulation toolkit suitable for performance evaluation of dataparallel applications like voice processing.  ...  Different DSP clusters are considered for the multiprocessor DSP simulation engine in which the DSP processors are grouped to cooperate.  ...  For example, in 2004 Intel announced it is moving its PC processor development towards multiprocessor solutions and away from a sole focus on increasing chip frequency.  ... 
doi:10.1109/mascots.2007.33 dblp:conf/mascots/Sedaghati-MokhtariBF07 fatcat:ktkzobc7o5c7xgyi7nqoldigxu

Advances in hardware design and implementation of signal processing systems [DSP Forum]

Shuvra Bhattacharyya, Jeff Bier, Wanda K. Gass, Ram K. Krishnamurthy, Edward A. Lee, Konstantinos Konstantinides
2008 IEEE Signal Processing Magazine  
processing systems on a chip (SoCs).  ...  A variety of commercial vendors offer single-chip multiprocessor DSP platforms, each with a collection of homogeneous or heterogeneous processors integrated on a single die, and this form of platform is  ... 
doi:10.1109/msp.2008.929838 fatcat:e5wcu4p5gzcavhybpykrti3hwy

Webpage-based benchmarks for mobile device design

Marc Somers, JoAnn M. Paul
2008 2008 Asia and South Pacific Design Automation Conference  
We then included this data in a set of simulations that also included models of a variety of scheduler types and heterogeneous multiprocessor architectures.  ...  Considering only modern-day content in webpages, we found that specialized architectures can improve performance up to 70% over a homogeneous multiprocessor composed of general purpose processors with  ...  What is significant about Figure 3 is that the content of the webpages is similar in form to the evaluation space of the chip, when the chip is viewed as a heterogeneous multiprocessor.  ... 
doi:10.1109/aspdac.2008.4484060 dblp:conf/aspdac/SomersP08 fatcat:e7c6trjdzfbn3f6os3evhcf5ji

Automatic Dsp Cache Memory Management And Fast Prototyping For Multiprocessor Image Applications

O. Deforges, Jean Franois Nezan, Mickael Raulet, Fabrice Urban
2006 Zenodo  
Publication in the conference proceedings of EUSIPCO, Florence, Italy, 2006  ...  A hand made data pre-fetch scheme can be used to temporarily store data into on-chip memory before it is needed, in a scratchpad way [1] .  ...  CONCLUSION We provide a way to easily use cache and automatically ensure cache coherence in a multiprocessor architecture.  ... 
doi:10.5281/zenodo.39900 fatcat:skf3b52qkzc5lhrfus3hrw3d74

Transforming Signal Processing Applications into Parallel Implementations

Ed F. Deprettre, Roger Woods, Ingrid Verbauwhede, Erwin de Kock
2007 EURASIP Journal on Advances in Signal Processing  
Bekooij describe an approach that uses multirate dataflow graphs (MRDFs) to schedule the tasks of a hard real-time streaming application onto a multiprocessor system-on-chip.  ...  The purpose of this special issue is to highlight work which addresses the limitations in mapping from the application model onto the architecture model for complex DSP systems.  ...  Bekooij describe an approach that uses multirate dataflow graphs (MRDFs) to schedule the tasks of a hard real-time streaming application onto a multiprocessor system-on-chip.  ... 
doi:10.1155/2007/95760 fatcat:3h3sdda4kzfgzkcxnxkptxdkvy

Verification Platform with ARM- and DSP-Based Multiprocessor Architecture for DVB-T Baseband Receivers

Koonshik Cho, June-Young Chang, Han-Jin Cho, Jun-Dong Cho
2008 ETRI Journal  
In this paper, we introduce a new verification platform with ARM-and DSP-based multiprocessor architecture.  ...  Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform.  ...  Therefore, to accommodate the flexibility of design changes, system on chip (SoC) implementation based on digital signal processors (DSPs) or general purpose processors (GPP) is becoming more important  ... 
doi:10.4218/etrij.08.0107.0129 fatcat:fghpc7jpdbccfpqcfnsczwsqfe

Design and implementation of an ordered memory access architecture

S. Sriram, E.A. Lee
1993 IEEE International Conference on Acoustics Speech and Signal Processing  
This paper describes a multiprocessor machine for realtime Digital Signal Processing that uses commercial programmable DSP chips.  ...  The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled.  ...  In [4] , the authors describe a DSP96002 based multi-DSP system with an "intelligent communication controller" implemented on a gate array for communicating through a high speed bus.  ... 
doi:10.1109/icassp.1993.319126 dblp:conf/icassp/SriramL93 fatcat:v376vz6i7bgvhjvjjn4ahntp24

Editorial

Mladen Berekovic, Andy D. Pimentel
2009 Journal of Signal Processing Systems  
In "Run-time Task Overlapping on Multiprocessor Platforms", Zhe Ma et al. address dynamic Pareto-optimal scheduling on multiprocessor systems.  ...  algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories.  ... 
doi:10.1007/s11265-008-0333-0 fatcat:7tkmyxohfrgvjpxdyaixevhelm

High-performance DSP architectures for intelligence and control applications

1991 IEEE Control Systems  
DSPs provide high computing power by employing a high level of on-chip parallelism, integrated hardware multipliers, carefully tailored instruction sets, memory organization schemes, hardware support for  ...  This paper describes the architectural features of DSPs for intelligence and control applications, and the node configuration of the IX-n generalpurpose neurocomputer, based on the commercially available  ...  In order to cope with the main advantage of microcontrollers, compact system design, some DSPs include EPROM memories and a significant amount of on-chip peripherals.  ... 
doi:10.1109/37.88592 fatcat:vhs764wo7vghvphh2gfkv3chka

The future of multiprocessor systems-on-chips

Wayne Wolf
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
A multiprocessor system-onchip includes embedded processors, digital logic, and mixedsignal circuits combined into a heterogeneous multiprocessor.  ...  Standards in communications, multimedia, networking, and other areas encourage the development of high-performance platforms that can support a range of implementations of the standard.  ...  Acknowledgments Thanks to Ahmed Jerraya, Alain Mellan, Faraydon Karim, Santanu Dutta, Pierre Paulin, and Phil Koopman for fruitful discussions about multiprocessor systems-on-chips.  ... 
doi:10.1145/996566.996753 dblp:conf/dac/Wolf04 fatcat:welw7ysflfgbhff6cvizv7mkee

Amdahl's Law Revisited for Single Chip Systems

JoAnn M. Paul, Brett H. Meyer
2007 International journal of parallel programming  
We show that a performance increase in one part of the system can negatively impact the overall performance of the system, in direct contradiction to the way Amdahl's Law is instructed.  ...  This, in turn, has relevance to the potential impacts of custom processors, system-level scheduling strategies and the way systems are partitioned.  ...  ACKNOWLEDGMENTS This work was supported in part by ST Microelectronics, and the National Science Foundation under Grants 0607934, 0606675, 0438948, and 0406384.  ... 
doi:10.1007/s10766-006-0028-8 fatcat:eovhu4x2kbbcziuhbthhn2l2dy

Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors

N.K. Bambha, S.S. Bhattacharyya
2005 IEEE Transactions on Parallel and Distributed Systems  
In this paper, we present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing  ...  In this case, communication on chip resembles a network.  ...  ACKNOWLEDGMENTS This research was supported in part by the US Defense Advanced Research Projects Agency (DARPA) under Contract number MDA972-00-1-0023, through Brown University.  ... 
doi:10.1109/tpds.2005.20 fatcat:fbtorglitjdsjdwyfxglrhoxhu

Compiler driven architecture design space exploration for DSP workloads: A study in software programmability versus hardware acceleration

Michael C. Brogioli, Joseph R. Cavallaro
2009 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers  
The paper uses a research compiler for architectural design space exploration to present comparisons between compiler generated scalable software programmable DSP architectures versus hardware acceleration  ...  It shows that scaled up compiler generated software programmable DSP architectures can be attractive alternatives to non-programmable hardware acceleration.  ...  ACKNOWLEDGMENT This work was supported in part by Nokia, Nokia Siemens Networks, Texas Instruments, Xilinx, and by NSF under grants CCF-0541363, CNS-0551692, CNS-0619767, EECS-0925942 and CNS-0923479.  ... 
doi:10.1109/acssc.2009.5470122 fatcat:6hiqu5mt6jeqvgoxqux56mneqy
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