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Programmable Logic Arrays [article]

Issam Damaj
2019 arXiv   pre-print
Programmable logic arrays (PLAs) are traditional digital electronic devices. A PLA is a simple programmable logic device (SPLD) used to implement combinational logic circuits.  ...  A PLA has a set of programmable AND gates, which link to a set of programmable OR gates to produce an output.  ...  The attractions of PLAs that brought them to mainstream engineers include their simplicity, relatively small circuit area, predictable propagation delay, and ease of development.  ... 
arXiv:1905.02074v1 fatcat:jzl25ljb5nemjn3igs32eey244

CAD Optimization Technique in Reconfigurable Computing System using Hybrid Architecture

Sunil Kr. Singh, R. K. Singh, M. P. S. Bhatia
2011 International Journal of Computer Applications  
The two main types of programmable logic devices, fieldprogrammable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology.  ...  architecture-specific optimization, physical synthesis, RT-level and behaviour-level synthesis.  ...  PLA/ PALs Programmable logic arrays (PLA) and programmable array logic (PAL) consist of a plane of AND-gates connected to a plane of OR-gates.  ... 
doi:10.5120/2935-3890 fatcat:trnoi6hhtbbi7lwejmsggf36da

Page 800 of Mathematical Reviews Vol. , Issue 81B [page]

1981 Mathematical Reviews  
Sasao, Tsutomu An application of multiple-valued logic to a design of programmable logic arrays.  ...  Author’s summary: “A three-level programmable logic array (three-level PLA) consists of three main parts, the D array, the AND array, and the OR array, and each of these arrays can be 81b:94072 + programmed  ... 

A New Field Programmable Gate Array: Architecture and Implementation

Hanjin Cho Cho, Young Hwan Bae Bae, Nak Woong Eum Eum, Inhag Park Park
1995 ETRI Journal  
Programmable logic devices (PLDs), which are arrays of programmable logic arrays (PLAs) with programmable interconnections, offer high speed but limited logic gate capacity and limited logic design flexibility  ...  Since the overall architecture consists of two-dimensional array of logic modules separated by horizontal and vertical channels, the physical size of a logic module and routing channels determine the array  ... 
doi:10.4218/etrij.95.0195.0023 fatcat:2ga4fjoeobakvhhtjjdlhdggbq

Page 5003 of Mathematical Reviews Vol. , Issue 80M [page]

1980 Mathematical Reviews  
Sasao, Tsutomu; Terada, Hiroaki 80m:94115 Multiple-valued logic and the design of programmable logic arrays with decoders.  ...  Authors’ summary: “A programmable logic array (PLA) with decoders consists of three parts: the fixed size decoders, the AND array, and the OR array.  ... 

Mask-programmable multiple-valued logic gate using resonant tunnelling diodes

H.L.E. Chan, M. Bhattacharya, P. Mazumder
1996 IEE Proceedings - Circuits Devices and Systems  
These gatcs can be used to implement cells of a gate array, with the benefit of having prograrnriiabk functionality and multiple-valued logic input and output lincs.  ...  The design of a I-input and a ?-input 4-valued logic gate is described.  ...  X = {xo, x I , .... x,,-, } with .Y taking on values from R = {0, 1, 2, One-input multiple valued logic gate 290 The structure of the proposed programmable 1-input 4-valued logic gatc is shown in Fig  ... 
doi:10.1049/ip-cds:19960571 fatcat:emr37dowlffctfxmd2vb3aplyu

On the optimal design of multiple-valued PLAs

T. Sasao
1989 IEEE transactions on computers  
In Type 2 PLA's, the body of the PLA is binary and the output is encoded as a multiple-valued logic value.  ...  This paper describes the design and analysis of three types of multiple-valued PLA's: 'lype 1 PLA's realize functions directly in the form of the MAX of MIN of literal functions and constants.  ...  The only two-valued circuits which are successfully designed by a complete automatic system and whose optimality is guaranteed are programmable logic arrays (PLA's) [ 181.  ... 
doi:10.1109/12.21150 fatcat:t7bbamzepzht7lbefyxlwbrg5i

Computing with nanoscale memory: Model and architecture

Somnath Paul, Swarup Bhunia
2009 2009 IEEE/ACM International Symposium on Nanoscale Architectures  
On the other hand, dense and periodic structures of most emerging nanodevices as well as their bi-stable nature make them amenable to large high-density memory array design.  ...  Unlike CMOS devices, however, majority of these devices are not suitable for implementing cascaded, irregular logic structure.  ...  consists of a dense 2-D memory array organized into multiple banks.  ... 
doi:10.1109/nanoarch.2009.5226362 dblp:conf/nanoarch/PaulB09 fatcat:kagx3f3j35fspfiamat7rqc6l4

Sizing of Processing Arrays for FPGA-Based Computation

Tom VanCourt, Martin Herbordt
2006 2006 International Conference on Field Programmable Logic and Applications  
order, multiple design parameters controlling different aspects of the computing structure, and interlocked usage of different hardware resources.  ...  Several factors complicate determination of the largest structure that will fit the FPGA: arrays that grow polynomially and trees that grow exponentially, coupled structures that grow in different polynomial  ...  FPGA resources The FPGA resources are simply the programmable logic, hardware multipliers, block RAMs, and other features accessible to the logic designer.  ... 
doi:10.1109/fpl.2006.311307 dblp:conf/fpl/CourtH06a fatcat:lohhka7p4zaldnwofchnvoavje

Compiler Optimizations for Adaptive EPIC Processors [chapter]

Krishna V. Palem, Surendranath Talla, Weng-Fai Wong
2001 Lecture Notes in Computer Science  
will be mapped to programmable logic.  ...  Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources.  ...  Like a typical Field Programmable Gate Array (FPGA), the MRLA is a two dimensional region of the processor die that is composed of programmable logic and interconnect blocks.  ... 
doi:10.1007/3-540-45449-7_18 fatcat:32lfxjsqofhk3m2h4mdtzza53u

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

Deliang Fan, Mrigank Sharad, Kaushik Roy
2014 IEEE transactions on nanotechnology  
A threshold logic gate (TLG) performs weighted sum of multiple inputs and compares the sum with a threshold.  ...  Field programmable SMTL gate arrays can operate at a small terminal voltage of ~50mV, resulting in ultra-low power consumption in gates as well as programmable interconnect networks.  ...  Next we discuss optimal pipelining and partitioning scheme for the mapping of large logic blocks on to the SMTL array. V. OPTIMAL PIPELINING AND PARTITIONING OF SMTL ARRAYS FOR LOGIC MAPPING A.  ... 
doi:10.1109/tnano.2014.2312177 fatcat:g26v3llgnvbbrf7w3sdbirfwp4

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter
2007 Microprocessors and microsystems  
They support pipelining of wire delays by providing pipeline registers at the intersections between wires in the reconfigurable cluster, retiming buffers at the inputs and outputs of logic blocks, and  ...  Wire delay is rapidly becoming a major bottleneck in reconfigurable systems, creating a significant gap between the clock rates of reconfigurable logic and custom circuits.  ...  Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the ONR, NSF, or AMD.  ... 
doi:10.1016/j.micpro.2006.03.001 fatcat:izat3z4hdrfg3lzeyapmr44e5y

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach

Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Multiple such computing elements communicate spatially through programmable interconnects.  ...  Reconfigurable computing frameworks such as field programmable gate array (FPGA) provide flexibility to map arbitrary applications.  ...  The basic structure of the FPGAs have continued to consist of configurable logic blocks (CLBs) and a programmable interconnect (PI) matrix [1] .  ... 
doi:10.1109/jetcas.2011.2165232 fatcat:tlnx3mng3remfghm4fgulfd27u

1983 Index IEEE Transactions on Computers Vol. C-32

1983 IEEE transactions on computers  
Weste, Neil, + , T-CAug 83731-744 easily testable programmable logic array design for detection of multiple faults.  ...  ., T-C Oct 83961-968 easily testable programmable logic array design for detection of multiple faults.  ... 
doi:10.1109/tc.1983.1676190 fatcat:xsogjoynp5dt7mqu6dy4tiodfq

MCUDA: An Efficient Implementation of CUDA Kernels for Multi-core CPUs [chapter]

John A. Stratton, Sam S. Stone, Wen-mei W. Hwu
2008 Lecture Notes in Computer Science  
We describe an implementation of this framework and demonstrate performance approaching that achievable from manually parallelized and optimized C code.  ...  Our framework consists of a set of source-level compiler transformations and a runtime system for parallel execution.  ...  Any opinions, findings, conclusions, or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the NSF.  ... 
doi:10.1007/978-3-540-89740-8_2 fatcat:wdg3yrut2jcxzpxunxaxz2zvky
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