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Multi-way partitioning of VLSI circuits

P. Agrawal, B. Narendran, N. Shivakumar
Proceedings of 9th International Conference on VLSI Design  
Partitioning is one of the critical phases of hierarchical design processes like VLSI design. Good partitioning techniques can positively in uence the performance and cost of a VLSI product.  ...  This paper proposes a partitioning algorithm with a new cost metric. Viewed from a VLSI layout point of view our cost metric minimizes the average delay per net.  ...  We show h o w our metric is more suitable to capture some of the physical attributes of multi-way partitioning in the VLSI context.  ... 
doi:10.1109/icvd.1996.489641 dblp:conf/vlsid/AgrawalNS96 fatcat:ssg5djmpavhtvocdsd7zi27dbi

DCCB and SCC based fast circuit partition algorithm for parallel SPICE simulation

Xiaowei Zhou, Yu Wang, Huazhong Yang
2009 2009 IEEE 8th International Conference on ASIC  
With the rapid scale growing of VLSI circuits, simulation speed and efficiency of CAD tool SPICE have turned out to be a bottleneck.  ...  Circuit partition is required to these strategies, but traditional partition algorithms encounter difficulties when facing VLSI circuits for parallel simulation.  ...  In this paper we introduce a new circuit partition algorithm specially designed for VLSI partition and multi-core parallel simulation, called DCCB (Direct Current Connected Blocks) and SCC (Strong Connected  ... 
doi:10.1109/asicon.2009.5351211 fatcat:lfyr2xtzvzek5frsjzv3siufcq

A Broad Review on Various VLSI CAD Algorithms for Circuit Partitioning Problems

R. Manikandan et al., R. Manikandan et al.,
2018 International Journal of Mechanical and Production Engineering Research and Development  
Circuit partitioning is the first and the most important step in the designing of VLSI circuits.  ...  The main intention of this paper is to provide a concise review of the VLSI CAD algorithms adopted for designing VLSI circuits.  ...  While genetic algorithms help in multi way partitioning of many types of VLSI circuits, hybrid algorithms which utilize PSO and GA were found to be better than any other optimization technique for minimizing  ... 
doi:10.24247/ijmperdfeb2018115 fatcat:kbnon3xtwncjbelzmumefqpbra

Multi-level sequential circuit partitioning for test vector generation for low power test in VLSI

VH Prathyush, K Somasundaram
2011 International Journal of Engineering, Science and Technology  
In this paper, we present a multi-level graph partitioning algorithm for circuit partitioning, which will minimize the number of test vectors during a low power test in VLSI circuits.  ...  Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit testing models.  ...  Finally, we understand that multi-level circuit partitioning algorithm is well suit for low power test of VLSI circuits.  ... 
doi:10.4314/ijest.v2i11.64556 fatcat:hiowg5duarcdlenegtlt7ysaty

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2010 IPSJ Transactions on System LSI Design Methodology  
Experiments showed that for four-way partitioned circuits, our method obtains an average system clock period 16.0% shorter than that of a conventional method.  ...  Multi-FPGA prototyping systems are widely used to verify logic circuit designs. To implement a large circuit using such a system, the circuit is partitioned into multiple FPGAs.  ...  Decomposition of a circuit into sub-circuits is called circuit partitioning. k-way partitioning of a circuit graph G(V, E) gives vertex sets V 1 , V 2 , . . . , V k such that V i = ∅, k i=1 V i = V , and  ... 
doi:10.2197/ipsjtsldm.3.81 fatcat:ykvklapzcvg33e3ad7yldmofbq

Combinatorial Optimization In Vlsi Hypergraph Partitioning Using Taguchi Methods

P.Subbaraj, S.Saravanasankar, S.Anand
2010 Zenodo  
Minimizing the number of interconnection between partitions, that is, the cut size of the circuit and 2. Balancing the area occupied by the partitions.  ...  This work addresses the methods to solve Very Large Scale Integration (VLSI) circuit partitioning problem with dual objectives, viz., 1.  ...  Acknowledgement The authors thank the Department of Science and Technology, New Delhi, Government of India, for the support under the project no: SR/S4/MS: 326/06.  ... 
doi:10.5281/zenodo.823861 fatcat:suvw37q6cjey7pt6kwvvqwv57a

Comparative Study Of Ant Colony And Genetic Algorithms For Vlsi Circuit Partitioning

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel
2009 Zenodo  
This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-partitioning.  ...  Results obtained show that Genetic algorithms out perform Ant Colony optimization technique when tested on the VLSI circuit bi-partitioning problem.  ...  A multi objective hMetis partitioning for simultaneous cutsize and circuit delay minimization is proposed [16] .  ... 
doi:10.5281/zenodo.1082181 fatcat:enswqwarcvbrfasm6x2qysrbi4

Evolutionary algorithms for VLSI multi-objective netlist partitioning

Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
2006 Engineering applications of artificial intelligence  
The interest in finding an optimal partition, especially in VLSI, has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance.  ...  The problem of partitioning appears in several areas ranging from VLSI, parallel programming to molecular biology.  ...  Special thanks to AbdulSubhan for assisting in the preparation of the manuscript.  ... 
doi:10.1016/j.engappai.2005.09.008 fatcat:thgb673b4redlbgz2naldcz57u

Graph clustering using multiway ratio cut (Software demonstration) [chapter]

Tom Roxborough, Arunabha Sen
1997 Lecture Notes in Computer Science  
In this paper we report on the implementation of a clustering algorithm based on the idea of ratio cut, a well known technique used for circuit partitioning in the VLSI domain.  ...  of graphs with a large number of nodes.  ...  Acknowledgements The authors wish to acknowledge Jay Noh for his work on the initial development of the clustering technique.  ... 
doi:10.1007/3-540-63938-1_71 fatcat:5of34wqu3bbwbhpyxjgymuyqqa

Clustering based acyclic multi-way partitioning

Eric S. H. Wong, Evangeline F. Y. Young, W. K. Mak
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
In this paper, we present a clustering based algorithm for acyclic multi-way partitioning.  ...  Experimental results showed that our algorithm compares favorably with the previous best acyclic multi-way partitioning algorithm in cut-size.  ...  INTRODUCTION Circuit partitioning is a critical stage in the VLSI design cycle.  ... 
doi:10.1145/764856.764860 fatcat:mmkrremddbdorlsmugzata5vsq

Clustering based acyclic multi-way partitioning

Eric S. H. Wong, Evangeline F. Y. Young, W. K. Mak
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
In this paper, we present a clustering based algorithm for acyclic multi-way partitioning.  ...  Experimental results showed that our algorithm compares favorably with the previous best acyclic multi-way partitioning algorithm in cut-size.  ...  INTRODUCTION Circuit partitioning is a critical stage in the VLSI design cycle.  ... 
doi:10.1145/764808.764860 dblp:conf/glvlsi/WongYM03 fatcat:hhkammiif5gmdp3krkedo4l3wy

Acyclic multi-way partitioning of Boolean networks

Jason Cong, Zheng Li, Rajive Bagrodia
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
In this paper, we present two efficient algorithms for the acyclic multi-way partitioning. One is a generalized FMbased algorithm.  ...  Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation.  ...  As one application, we have evaluated the impact of different acyclic multi-way partitioning algorithms on circuit simulation.  ... 
doi:10.1145/196244.196609 dblp:conf/dac/CongLB94 fatcat:pmg2z2aot5ebdjz7qtkiryoqly

A 1–190MSample/s 8–64 tap energy-efficient reconfigurable FIR filter for multi-mode wireless communication

Farhana Sheikh, Melinda Mill, Brian Richards, Dejan Markovic, Borivoje Nikolic
2010 2010 Symposium on VLSI Circuits  
A 6way parallel, 2-way time-multiplexed architecture with circuits for memory offset binary coding and memory partitioning enable input wordlength and tap configurability with 1-190MSample/s throughput  ...  An energy-efficient reconfigurable distributed-arithmetic FIR filter for multi-mode wireless communication is fabricated in 7M1P 90nm CMOS and occupies 1.5mm 2 .  ...  Acknowledgments The authors acknowledge C2S2, SRC and Intel Corp. for funding this research, ST Microelectronics for chip fabrication, and contributions of students, faculty and sponsors of BWRC and NSF  ... 
doi:10.1109/vlsic.2010.5560297 fatcat:aijqb5etnrcvdlde3b24a5fmoq

Algorithms for CAD Tools VLSI Design [chapter]

K.A. Sumithra
2012 VLSI Design  
Circuit partitioning concept VLSI circuit partitioning is a vital part of physical design stage.  ...  VLSI circuit partitioning is a vital part of the physical design stage.  ...  The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic  ... 
doi:10.5772/37959 fatcat:gyanbrku5ndgvl6fz2ybfswtvi

Partitioning of VLSI circuits and systems

Frank M. Johannes
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning problems to be solved on all levels of abstraction.  ...  The rapidly increasing size of the designs will make good partitioning tools even more essential in the future.  ...  Multi-way partitionings can be generated by recursively solving two-way partitioning problems.  ... 
doi:10.1145/240518.240535 dblp:conf/dac/Johannes96 fatcat:wdgj4exw4zfw5mmaygdmlwwwmy
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