Filters








394 Hits in 6.2 sec

Multi-way VLSI Circuit Partitioning Based On Dual Net Representation

J. Cong, W. Lubio, N. Shivakumur
IEEE/ACM International Conference on Computer-Aided Design  
for multi-way circuit partitioning based on dual net transformation.  ...  In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm  ...  Acknowledgments The authors would like to thank Phil Kuekes and Greg Snider at Hewlett-Packard Laboratory for providing benchmark circuits.  ... 
doi:10.1109/iccad.1994.629744 dblp:conf/iccad/CongLS94 fatcat:wjzmi3fjwngatnvs7w27igigwa

Multiway VLSI circuit partitioning based on dual net representation

J. Cong, W. Juan Labio, N. Shivakumar
1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
for multi-way circuit partitioning based on dual net transformation.  ...  In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm  ...  Acknowledgments The authors would like to thank Phil Kuekes and Greg Snider at Hewlett-Packard Laboratory for providing benchmark circuits.  ... 
doi:10.1109/43.494703 fatcat:mvlckfqmorgnfnn6xzpvqa4xqq

Comparative Study Of Ant Colony And Genetic Algorithms For Vlsi Circuit Partitioning

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel
2009 Zenodo  
Results obtained show that Genetic algorithms out perform Ant Colony optimization technique when tested on the VLSI circuit bi-partitioning problem.  ...  This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-partitioning.  ...  RESULTS AND DISCUSSION The performance of the ACO and GA algorithms in tested on circuit partitioning instances (net lists) given on the MARCO GSRC VLSI CAD Bookshelf website [30] .  ... 
doi:10.5281/zenodo.1082181 fatcat:enswqwarcvbrfasm6x2qysrbi4

Combinatorial Optimization In Vlsi Hypergraph Partitioning Using Taguchi Methods

P.Subbaraj, S.Saravanasankar, S.Anand
2010 Zenodo  
This work addresses the methods to solve Very Large Scale Integration (VLSI) circuit partitioning problem with dual objectives, viz., 1.  ...  Minimizing the number of interconnection between partitions, that is, the cut size of the circuit and 2. Balancing the area occupied by the partitions.  ...  Later Cong.J (1994) developed k-way net based multi way partitioning algorithm to produce better quality solutions than the FM algorithm but only for smaller size problems.  ... 
doi:10.5281/zenodo.823861 fatcat:suvw37q6cjey7pt6kwvvqwv57a

Genetic Algorithm Based Approach To Circuit Partitioning

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel
2010 International Journal of Computer and Electrical Engineering  
In this paper multiway circuit partitioning of circuits using Genetic Algorithms has been attempted.  ...  Results obtained show the versatility of the proposed method in solving NP hard problems like circuit partitioning.  ...  Kernighan and Lin [2] proposed a heuristic for two-way partitioning which was the first iterative algorithm based on swapping of vertices.  ... 
doi:10.7763/ijcee.2010.v2.136 fatcat:vr5blsoq4jewdgp2lf6mappzyy

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis

Sheldon X.-D. Tan, C.-J.Richard Shi
2003 Integration  
This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs).  ...  We show that the problem can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints, and be solved in two phases by connectivity-oriented initial clustering and  ...  Acknowledgements The authors thank three reviewers for their valuable and constructive comments of this work that improve the representation of this paper.  ... 
doi:10.1016/s0167-9260(03)00002-6 fatcat:5k7l7xscdrei3dp4qhun7rt3au

Hypergraph Partitioning and Clustering [chapter]

David Papa, Igor Markov
2007 Handbook of Approximation Algorithms and Metaheuristics  
One way to achieve this is through recursive calls to hypergraph partitioning on a hypergraph representation of the matrix.  ...  The hypergraph corresponding to a logic circuit directly maps gates to vertices and nets to hyperedges. The dual of this hypergraph is sometimes used as well.  ...  NumPins on line 3 of example.nets specifies the sum of hyperedge degrees. example.blk specifies balance constraints, the sum of vertex weights in each partition must be 4 ± 25%.  ... 
doi:10.1201/9781420010749.ch61 fatcat:a2d6efybyffzfpopmvmgpi7ghe

Tutorial on VLSI Partitioning

Sao-Jie Chen, Chung-Kuan Cheng
2000 VLSI design (Print)  
The tutorial introduces the partitioning with applications to VLSI circuit designs.  ...  The problem formulations include two-way, multiway, and multi-level partitioning, partitioning with replication, and performance driven partitioning.  ...  Multi-way Partitioning For multi-way partitioning, we discuss a k-way partitioning with ®xed size constraints and a cluster ratio cut.  ... 
doi:10.1155/2000/53913 fatcat:rjeorq3akjcbneo5mjdzbz4ywy

Recent directions in netlist partitioning: a survey

Charles J Alpert, Andrew B Kahng
1995 Integration  
Algorithms based on geometric representations embed the circuit netlist in some type of geometry", e.g, a 1-dimensional linear ordering or a multi-dimensional vector space; the embeddings are commonly  ...  We discuss the traditional min-cut and ratio cut bipartitioning formulations along with multi-way extensions and newer problem formulations, e.g., constraint-driven partitioning for FPGAs and partitioning  ...  Multi-Way P artitioning Formulations A multi-way partitioning is a k-way partitioning with k 2.  ... 
doi:10.1016/0167-9260(95)00008-4 fatcat:337iiybf3vhuzlybuub3wlvfiy

Memetic Multilevel Hypergraph Partitioning [article]

Robin Andre, Sebastian Schlag, Christian Schulz
2018 arXiv   pre-print
Hypergraph partitioning has a wide range of important applications such as VLSI design or scientific computing.  ...  Compared to the state-of-the-art hypergraph partitioning tools hMetis, PaToH, and KaHyPar, our new algorithm computes the best result on almost all instances.  ...  Evolutionary Hypergraph Partitioning. Saab and Rao [47] present an evolution-based approach for solving a k-way multi-objective, multi-constraint hypergraph partitioning problem.  ... 
arXiv:1710.01968v2 fatcat:4msekcj2nfa7bgghtqbsr5uxeu

Hypergraph Partitioning through Vertex Separators on Graphs [article]

Enver Kayaaslan, Ali Pinar, Umit V. Catalyurek, Cevdet Aykanat
2011 arXiv   pre-print
Specifically, we investigate how to solve the hypergraph partitioning problem by seeking a vertex separator on its net intersection graph (NIG), where each net of the hypergraph is represented by a vertex  ...  This work addresses one method for this trade-off by solving the hypergraph partitioning problem by finding vertex separators on graphs.  ...  Other circuit representation models were also proposed and used in the VLSI literature including dual hypergraph, cliquenet graph (CNG) and net-intersection graph (NIG) [2] .  ... 
arXiv:1103.0106v1 fatcat:i76667zblzemxblfny5xbyp26i

Efficient optimization by modifying the objective function: applications to timing-driven VLSI layout

R. Baldick, A.B. Kahng, A. Kennings, I.L. Markov
2001 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
functions e.g., VLSI placement with linear wirelength.  ...  ., the modi cation must have a bounded e ect on the quality of the solution.  ...  based on min-cost ows and graphbased simplex methods.  ... 
doi:10.1109/81.940185 fatcat:fe3hcuuhozgprlnqch7enlsexu

New spectral methods for ratio cut partitioning and clustering

L. Hagen, A.B. Kahng
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Finally, we discuss the very natural intersection graph representation of the circuit netlist as a basis for partitioning, and propose a heuristic based on spectral ratio cut partitioning of the netlist  ...  Partitioning of circuit netlists is important in many phases of VLSI design, ranging from layout to testing and hardware simulation.  ...  Examples include: a) multi-way partitioning, particularly when the sizes of the partitions are not known a priori; b) floorplanning or constructive placement; and c) situations when the circuit design  ... 
doi:10.1109/43.159993 fatcat:jostndvucnb4phxnuwucmf2wty

Network Flow-Based Refinement for Multilevel Hypergraph Partitioning [article]

Tobias Heuer, Peter Sanders, Sebastian Schlag
2018 arXiv   pre-print
We present a refinement framework for multilevel hypergraph partitioning that uses max-flow computations on pairs of blocks to improve the solution quality of a k-way partition.  ...  The framework generalizes the flow-based improvement algorithm of KaFFPa from graphs to hypergraphs and is integrated into the hypergraph partitioner KaHyPar.  ...  This approach significantly reduces the size of flow networks derived from VLSI hypergraphs, since most of the nets in a circuit are graph edges.  ... 
arXiv:1802.03587v2 fatcat:n4poiwo7ivaovpuk7xhnskk7l4

Constraint-based watermarking techniques for design IP protection

A.B. Kahng, J. Lach, W.H. Mangione-Smith, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
functions e.g., VLSI placement with linear wirelength.  ...  ., the modi cation must have a bounded e ect on the quality of the solution.  ...  based on min-cost ows and graphbased simplex methods.  ... 
doi:10.1109/43.952740 fatcat:l22bt26shvbrfkw4shw7p2biai
« Previous Showing results 1 — 15 out of 394 results