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Multi-terminal nets do change conventional wire length distribution models

Dirk Stoobandt
<span title="">2001</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/alydd4pwozg5bi5jtatwthbt6q" style="color: black;">Proceedings of the 2001 international workshop on System-level interconnect prediction - SLIP &#39;01</a> </i> &nbsp;
The multi-terminal net model is then used to estimate the wire length distribution in two cases: (i) the distribution of source-sink pairs for applications of delay estimation and (ii) the distribution  ...  Conventional models for estimating wire lengths in computer chips use Rent's rule to estimate the number of terminals between sets of gates.  ...  CONCLUSION Conventional wire length estimation models do not properly take multi-terminal nets into account.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/368640.368679">doi:10.1145/368640.368679</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/slip/Stoobandt01.html">dblp:conf/slip/Stoobandt01</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nlkhobhxk5hcpgrce2ycwugljm">fatcat:nlkhobhxk5hcpgrce2ycwugljm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829072701/http://www.cl.cam.ac.uk/research/srg/han/ACS-P35/readinglist/stroobandt-slip01.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/59/86/59867a5029f5e97c8e945bbd4b743efb8e6624c0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/368640.368679"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

M/sup 2/R: multilayer routing algorithm for high-performance MCMs

Jun Dong Cho, Kuo-Feng Liao, S. Raje, M. Sarrafzadeh
<span title="">1994</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/a2sy5llz7rchfdd7zku3k2hthy" style="color: black;">IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications</a> </i> &nbsp;
First we introduce the Pin Pre-wiring and Redktnbution Problem, which redistributes the pins or prewired subnets uniformly over the MCM substrate using pin redistribution layers.  ...  One strategy is to apply single-layer routing iteratively until a% of the nets are routed, then route the remaining (100a) % nets by xy planepair routing process.  ...  However, in our multilayer routing model for MCMs, we generalize the model by allowing multiple wiring tracks between adjacent vias. The generalized model has been used terminal nets.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/81.285679">doi:10.1109/81.285679</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7a6qwofqlnftjfoijjechl4gii">fatcat:7a6qwofqlnftjfoijjechl4gii</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20110401014717/http://vada.skku.ac.kr/Research/published/00285679.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/da/d7/dad7e98bfadd8b527b34c6cc5b3450ae86e74df4.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/81.285679"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Simultaneous floorplanning and resource binding

Azadeh Davoodi, Ankur Srivastava
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC &#39;05</a> </i> &nbsp;
Traditional approaches iteratively perform floorplanning and resource binding while using crude deterministic wire-length estimates like bounding box (since we do not have routing information for inter  ...  In this work we model the wirelengths as probability distributions and propose a novel probabilistic optimization methodology.  ...  Using the wire length distribution model explained in section III, the length probability distributions of the nets are obtained for each binding.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1120725.1120952">doi:10.1145/1120725.1120952</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/DavoodiS05.html">dblp:conf/aspdac/DavoodiS05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nlz5papwozdljhdcql7jbsacd4">fatcat:nlz5papwozdljhdcql7jbsacd4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060906204230/http://www.ece.wisc.edu/~adavoodi/papers/aspdac05_1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/03/f9/03f9e407dd9c33e10dc640092ca61302035df1b1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1120725.1120952"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Spatially distributed 3D circuit models

Michael Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 42nd annual conference on Design automation - DAC &#39;05</a> </i> &nbsp;
net-to-net approach.  ...  Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather than using the traditional  ...  Loop inductances, which are proportional to the difference L-M, do not change much and so the subsequent circuit solution is accurate.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1065579.1065621">doi:10.1145/1065579.1065621</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/BeattieZDK05.html">dblp:conf/dac/BeattieZDK05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3bdpgc7phjgwleftua6cev5xhu">fatcat:3bdpgc7phjgwleftua6cev5xhu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170815004247/http://www.cecs.uci.edu/~papers/dac05/papers/2005/dac05/pdffiles/p153.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/db/b7/dbb7f876244d0c5720721e594fb9bfdba5ab7b6c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1065579.1065621"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit
<span title="">2013</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pboyhm4o35h5zf2v7usd2ygk5a" style="color: black;">Proceedings of the 2013 ACM international symposium on International symposium on physical design - ISPD &#39;13</a> </i> &nbsp;
Additionally, wire planning of the on-chip interconnect is performed, as its topology and organization affect the physical layout of the system.  ...  Traditional algorithms for floorplanning and wire planning are customized to include physical constraints specific for tiled hierarchical architectures.  ...  All the global interconnect nets have this property. Wire length constraints. Due to performance reasons, certain critical nets must have a wire length constraint.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2451916.2451920">doi:10.1145/2451916.2451920</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ispd/CortadellaPNP13.html">dblp:conf/ispd/CortadellaPNP13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ufzyr2nvlzg7zd4og7af4oe46u">fatcat:ufzyr2nvlzg7zd4og7af4oe46u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809184948/http://www.cs.upc.edu/~jordicf/Research/gavina/BIB/files/ispd2013.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e8/b4/e8b456671f7f7463cc3cb893fc1f7b9a395d1c0c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2451916.2451920"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design

Jingyu Xu, X. Hong, Tong Jing, Yang Yang
<span title="">2006</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l3azs6sc2zakpnimahudrlgqlu" style="color: black;">IEEE transactions on circuits and systems - 2, Analog and digital signal processing</a> </i> &nbsp;
In the case of multi-terminal nets, the delay is formulated as (1) (2) Where node is the source, node is the predecessor node of node , is the Sakurai delay from source to . is the wire length from to  ...  Delay Model We adopt the distributed RC delay model developed by Sakurai [12] for delays.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcsii.2005.862041">doi:10.1109/tcsii.2005.862041</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/us3u6hhdqvfcrks5ghvy4cpanu">fatcat:us3u6hhdqvfcrks5ghvy4cpanu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20070824034922/http://www.ee.ucla.edu/~tomjing/TJing-JPapers/J12-TCASII2006-TObs-JYXu-01618903.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a5/2a/a52a7a1f5241c9bbe3d2291ce372bb1cc35c6745.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcsii.2005.862041"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A predictive distributed congestion metric and its application to technology mapping

Rupesh S. Shelar, Sachin S. Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
<span title="">2004</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pboyhm4o35h5zf2v7usd2ygk5a" style="color: black;">Proceedings of the 2004 international symposium on Physical design - ISPD &#39;04</a> </i> &nbsp;
This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization.  ...  Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology  ...  Multi-terminal nets are modeled using cliques for the congestion computation, and congestion contribution of each edge is scaled by a factor of ¾ Ò, where Ò is the number of edges.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/981066.981111">doi:10.1145/981066.981111</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ispd/ShelarSSW04.html">dblp:conf/ispd/ShelarSSW04</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bunynkrfonendpun52374h5rvi">fatcat:bunynkrfonendpun52374h5rvi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100618120229/http://www.ece.umn.edu/~sachin/conf/ispd04rs.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cb/bd/cbbdbef88d437bfddcbe8542a422ee39151a0f6f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/981066.981111"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Inter-Networking Heterogeneous Embedded Networks through Universal Bus

Sairohith S
<span title="2020-04-25">2020</span> <i title="The World Academy of Research in Science and Engineering"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/naqzxq5hurh2bp2pnvwitnnx44" style="color: black;">International Journal of Advanced Trends in Computer Science and Engineering</a> </i> &nbsp;
Distributed embedded systems can be developed either through wired or wireless based networking.  ...  Interconnecting the Individual networks can be done using bridges, Single master interface, and Multi Master Interface.  ...  A different gadget can be structured and built up that has the capacity of doing convention change utilizing numerous Microcontroller based frameworks, fast double port RAM information sharing innovation  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.30534/ijatcse/2020/80922020">doi:10.30534/ijatcse/2020/80922020</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wptjfeifwff37ooznfytrqcbye">fatcat:wptjfeifwff37ooznfytrqcbye</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220224231936/http://www.warse.org/IJATCSE/static/pdf/file/ijatcse80922020.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/94/07/94076d3dde764e1ccdfed0f5e110bbcc67fd7616.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.30534/ijatcse/2020/80922020"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Routing for manufacturability

Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
<span title="">1994</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 31st annual conference on Design automation conference - DAC &#39;94</a> </i> &nbsp;
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed.  ...  Based on this analysis, a general routing cost function is presented, in which the manufacturability of a net is taken into account in conjunction with the traditional routing objectives.  ...  Thus the conventional cost function is modeled as a minimum length cost function.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/196244.196435">doi:10.1145/196244.196435</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/XueHJ94.html">dblp:conf/dac/XueHJ94</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lzoikqxcurfgbazxbymbrxudji">fatcat:lzoikqxcurfgbazxbymbrxudji</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20031106011510/http://www.sigda.org:80/Archives/ProceedingArchives/Dac/Dac94/papers/1994/dac94/pdffiles/24_6.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ae/dc/aedcbc8a7bf9b2ceac2018aab6624b63e6373f56.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/196244.196435"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Design of FPGAs with Area I/O for Field Programmable MCM

V. Maheshwari, J. Darnauer, J. Ramirez, W.W. Dai
<span title="">1995</span> <i title="IEEE"> Third International ACM Symposium on Field-Programmable Gate Arrays </i> &nbsp;
If we adopt the convention that the IOs in the area-IO case are distributed evenly inside the logic blocks in the core, then the lengths are drawn from a random process equivalent t o L int : l ext;aio  ...  Ignoring the discrete nature of the placement, the expected value of the internal net length depends on the number of terminals and is proportional to the array size.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fpga.1995.241858">doi:10.1109/fpga.1995.241858</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6cxiuvdrqzcb3m7y6m3kth3jau">fatcat:6cxiuvdrqzcb3m7y6m3kth3jau</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20040911221730/http://www.sigda.org:80/Archives/ProceedingArchives/Compendiums/papers/1995/fpga95/pdffiles/1c.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2a/4e/2a4e0afe55542242a950c0057421d92bbf594cbc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fpga.1995.241858"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

Hao Tang, Genggeng Liu, Xiaohua Chen, Naixue Xiong
<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design.  ...  Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.  ...  A formulation for multi-terminal nets routing to multicommodity flow model was conducted by Raghavan and Thompson [139] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2020.2986138">doi:10.1109/access.2020.2986138</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nqpdbybucjembl4iztn67l4fgi">fatcat:nqpdbybucjembl4iztn67l4fgi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201108053407/https://ieeexplore.ieee.org/ielx7/6287639/8948470/09057662.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/52/5e/525ecb3a09dad0f5b1d26d6fa1e5c3d8d15b06d1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2020.2986138"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>

Early stage power management for 3D FPGAs considering hierarchical routing resources

Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki Murakami
<span title="">2013</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cuck3arl5zcl5nv2jjpeyumj44" style="color: black;">Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI &#39;13</a> </i> &nbsp;
Our results show that there is a scope for achieving desired distribution of power among the layers well before the placement with reasonable deviation in estimation and proves that our methodology is  ...  including multi-terminal nets  ...  As shown in Fig. 4 (b), we get the probability of each net to have a specific length (wirelength distribution) for both 2D and 3D nets separately using Stroobandt's model [14] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2483028.2483055">doi:10.1145/2483028.2483055</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/glvlsi/NunnaMM13.html">dblp:conf/glvlsi/NunnaMM13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2nhq3j22vnf2zk7rlw44xqt2cq">fatcat:2nhq3j22vnf2zk7rlw44xqt2cq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20150502052022/http://www.c.csce.kyushu-u.ac.jp/~farhad/Published%20version-gls084-Nunna.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c8/0c/c80cc3636eb52c1088bfc5db0c544c8c4f7cbb98.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2483028.2483055"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Design methodology of a 200MHz superscalar microprocessor

Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura
<span title="">1998</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 35th annual conference on Design automation conference - DAC &#39;98</a> </i> &nbsp;
We performed layout trials using preliminary netlists and evaluated back annotated wiring lengths for inter-module nets and estimate average wiring length for internal nets of the module.  ...  Direct signal nets not to run near some critical clock nets. (8) Perform delay/skew analysis with wiring load because a skew value is very sensitive to adjacent wiring capacitance. (9)Do final modification  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277108">doi:10.1145/277044.277108</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/HattoriNSNUTS98.html">dblp:conf/dac/HattoriNSNUTS98</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/g4z4wiwbufed3nqc6r6uc5fecq">fatcat:g4z4wiwbufed3nqc6r6uc5fecq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706151820/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1998/dac98/pdffiles/14_4.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/92/21/9221d81a1b5cbb1ece71bb36d8edd392b2c06191.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277108"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A predictive distributed congestion metric with application to technology mapping

R.S. Shelar, S.S. Sapatnekar, P. Saxena, Xinning Wang
<span title="">2005</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;
This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization.  ...  For delay-oriented mapping, our algorithm improves track overflows by 20%, on an average, in addition to preserving or improving the delay, as compared to the conventional method.  ...  Multi-terminal nets are modeled using cliques for the congestion computation, and congestion contribution of each edge is scaled by a factor of ¾ Ò, where Ò is the number of edges.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2005.846368">doi:10.1109/tcad.2005.846368</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cri44bfsjzgh7asr5l5w66he6i">fatcat:cri44bfsjzgh7asr5l5w66he6i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100618090745/http://www.ece.umn.edu/~sachin/jnl/tcad05rs.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9c/9b/9c9b4c7db7882c642cfafc97fc21758c29381a80.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2005.846368"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Physical hierarchy generation with routing congestion control

Chin-Chih Chang, Jason Cong, Zhigang (David) Pan
<span title="">2002</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pboyhm4o35h5zf2v7usd2ygk5a" style="color: black;">Proceedings of the 2002 international symposium on Physical design - ISPD &#39;02</a> </i> &nbsp;
Moreover, the congestion driven mPG improves 50% wiring overflow with 5% larger bounding box wire length but 3 − 6% shorter routing wire length measured by graph based A-tree.  ...  Experimental results show that, compared to GORDIAN-L , the wire length driven mPG is 3−6.5 times faster and generates slightly better wire length for test circuits larger than 100K cells.  ...  In [8] , the wiring demand of a net is modeled by a weighted bounding box length. The wiring demand estimation can be fast, though it may be inaccurate.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/505388.505399">doi:10.1145/505388.505399</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ispd/ChangCP02.html">dblp:conf/ispd/ChangCP02</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mu3etkgsdbgefd4n4s6zlkze7e">fatcat:mu3etkgsdbgefd4n4s6zlkze7e</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20040507140259/http://ballade.cs.ucla.edu:80/~yuanxin/publication/ispd02.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/6c/9f/6c9f5d87c6ca296d716f56986ce418917169222f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/505388.505399"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>
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