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On-Chip Hardware Accelerator For DSP Applications

2019 International journal of recent technology and engineering  
This kind of multi core platform can boost multimedia applications through parallel processing.  ...  This article presents new hardware accelerating platform comprised of heterogeneous multi core processing elements integrated on single chip FPGA.  ...  So, design of multi core heterogeneous multitasking systems have got significant demand in both industry and academia. II.  ... 
doi:10.35940/ijrte.c6079.098319 fatcat:gtssfhzxurfv7bbg7sovvp67si

From network sharing to multi-tenancy: The 5G network slice broker

Konstantinos Samdanis, Xavier Costa-Perez, Vincenzo Sciancalepore
2016 IEEE Communications Magazine  
This paper provides an overview of the 3GPP standard evolution from network sharing principles, mechanisms and architectures to future on-demand multi-tenant systems.  ...  The ever-increasing traffic demand is pushing network operators to find new cost-efficient solutions towards the deployment of future 5G mobile networks.  ...  In the core of our proposed on-demand multi-tenant network architecture lies a logically centralized monitoring and control entity defined as 5G Network Slice Broker providing admission control for incoming  ... 
doi:10.1109/mcom.2016.7514161 fatcat:3fmprracujdt3j3rwe25ytj5ri

Advances in the Design and Implementation of a Multi-tier Architecture in the GIPSY Environment with Java

Bin Han, Serguei A. Mokhov, Joey Paquet
2010 2010 Eighth ACIS International Conference on Software Engineering Research, Management and Applications  
used to implement the Demand Migration Framework (DMF) in order to streamline distributed execution of hybrid intensional-imperative programs using Java.  ...  We present advances in the software engineering design and implementation of the multi-tier run-time system for the General Intensional Programming System (GIPSY) by further unifying the distributed technologies  ...  All TAs must implement this interface. This is a super-interface for the use by the engine and the multi-tier architecture.  ... 
doi:10.1109/sera.2010.40 dblp:conf/sera/HanMP10 fatcat:ftapcorcr5bgtc26mbaeck5vaq

An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip

Lijing ZHU, Kun WANG, Duan ZHOU, Liangkai LIU, Huaxi GU
2018 IEICE transactions on information and systems  
An algorithm is developed to optimize the low congestion multi-ring topology.  ...  In this paper, we proposed an algorithm to build a low congestion multi-ring architecture for optical network-on-chip without additional wavelength or scheduling overhead.  ...  Figure 3 illustrates the multi-ring interface, which consists of three modules, namely, IP core, interface, and ring buses.  ... 
doi:10.1587/transinf.2017edp7330 fatcat:57ujbqrfjrdh3hhkdcb4kzn3qa

Hardware and Software Development of Multi-channel Environment Parameter Tester

Shuangshuang Cheng, Yongqing Wang, Shuhan Li, Chunhui Lu, Xiaoqi Zhou, Qisheng Zhang
2016 DEStech Transactions on Engineering and Technology Research  
A multi-channel environment parameter tester is developed in order to improve the simple testing function of domestic environment monitoring instrument.  ...  The test results approves that all channels of multi-channel environment parameter tester designed are working normally, and the environmental data collected is real and believable.  ...  interface.  ... 
doi:10.12783/dtetr/icmite20162016/4561 fatcat:nnapq6b2lzaf5cwme3mx34ithu

3D Embedded multi-core: Some perspectives

F Clermidy, F Darve, D Dutoit, W Lafi, P Vivet
2011 2011 Design, Automation & Test in Europe  
In this paper, we investigate three promising perspectives for short to medium terms adoption of such technology in high-end System-on-Chip built around multi-core architectures: the wide bus concept will  ...  We show that an efficient implementation provides an available bandwidth outperforming classical interfaces.  ...  The new interface between the Multi-core SoC and the interposer can then be limited to an efficient and unique interconnect like the 3D NoC.  ... 
doi:10.1109/date.2011.5763213 dblp:conf/date/ClermidyDDLV11 fatcat:ekzwiuwtpjhh7nelyycys6whyq

Orchestration of Crosshaul slices from federated administrative domains

Luis M. Contreras, Carlos J. Bernardos, Antonio de la Oliva, Xavier Costa-Perez, Riccardo Guerzoni
2016 2016 European Conference on Networks and Communications (EuCNC)  
future demands.  ...  This paper proposes to develop the concept of multi-domain Crosshaul by enabling the dynamic request of Crosshaul slices through a multi-provider exchange.  ...  The demand of dynamic resource allocation involve networking but also computing facilities, in order to flexibly deploy services and host content at the edge, thus saving core network capacity and decreasing  ... 
doi:10.1109/eucnc.2016.7561036 dblp:conf/eucnc/ContrerasBOCG16 fatcat:rd473dtlencjrdnb4natqgh25i

Design and implementation of digital TV widget for Android on multi-core platform

Yu-Sheng Lu, Chin-Ho Lee, Hung-Yen Weng, Yueh-Min Huang
2010 2010 International Computer Symposium (ICS2010)  
processors of the multi-core system with Android.  ...  In the mode of a multi-core cooperative work, the work requiring greater mathematical operations, such as video decoding, is assigned to a cooperative processor, which is specially designed for mathematical  ...  Android operating system in a multi-core framework.  ... 
doi:10.1109/compsym.2010.5685447 fatcat:msn7zsdiqfe37j4zqz5ndoum2y

H.264/AVC framework for multi-core embedded video encoders

Tiago Dias, Nuno Roma, Leonel Sousa
2010 2010 International Symposium on System on Chip  
A highly modular framework for developing parallel H.264/AVC video encoders in multi-core systems is presented.  ...  Such method takes into consideration not only the data structures required to implement the considered operations, but also the available interface of the target hardware structure.  ...  Fig. 2 .Fig. 3 . 23 Memory map of the multi-core processor for the APB peripherals and ME IP core user interface. Block diagram of the APB ME IP core.  ... 
doi:10.1109/issoc.2010.5625538 dblp:conf/issoc/DiasRS10 fatcat:6dtcwebrxvfxdmae2z2bzdhgpm

Bursting Data between Data Centers: Case for Transport SDN

Abhinava Sadasivarao, Sharfuddin Syed, Ping Pan, Chris Liou, Inder Monga, Chin Guok, Andrew Lake
2013 2013 IEEE 21st Annual Symposium on High-Performance Interconnects  
, multi-layer, multi-domain issues that hybrid cloud providers face.  ...  The proposed programmable architecture abstracts a core transport node into a programmable virtual switch that leverages the OpenFlow protocol for control.  ...  MODES OF OPERATION We have so far described how SDN for core transport networks can provide an alternative to multi-layer control plane interaction.  ... 
doi:10.1109/hoti.2013.20 dblp:conf/hoti/SadasivaraoSPLMGL13 fatcat:ktrwy74rl5g5vpokdj264ugiqi

Distributed High-Performance Parallel Mesh Generation with ViennaMesh [chapter]

Jorge Rodríguez, Josef Weinbub, Dieter Pahr, Karl Rupp, Siegfried Selberherr
2013 Lecture Notes in Computer Science  
Conventional mesh generation tools struggle to keep up with the increased workload, as they do not scale with the availability of, for example, multi-core CPUs.  ...  We present a parallel mesh generation approach for multi-core and distributed computing environments based on our generic meshing library ViennaMesh and on the Advancing Front mesh generation algorithm  ...  In this work we investigate a self-consistent volume mesh generation approach for multi-core CPUs and distributed computing environments based on the Message Passing Interface (MPI).  ... 
doi:10.1007/978-3-642-36803-5_44 fatcat:3z2pc2fforgrpnvzzoujddigga

A Generic Multi-layer Network Optimization Model with Demand Uncertainty [chapter]

Uwe Steglich, Thomas Bauschert, Christina Büsing, Manuel Kutschka
2013 Lecture Notes in Computer Science  
The goal is to minimize the overall network equipment costs containing basic node costs and interface costs while guarding against variations of the traffic demand.  ...  In this work we introduce a mixed integer linear program (MILP) for multi-layer networks with demand uncertainty.  ...  For our calculations we use a conventional PC with multi-core CPU (Intel R Core TM i7-3930K CPU @ 3.20GHz) and 64 GBytes of memory. Operating system is Ubuntu in version 11.04.  ... 
doi:10.1007/978-3-642-40552-5_2 fatcat:7iseirty7bcg5hsokwhyp2m3be

On the Feasibility of a Codelet Based Multi-core Operating System

Jack B. Dennis
2014 2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing  
We believe it is feasible to build a multi-core operating system that implements virtual memory, and honors the principles of modular software construction, using runtime software that executes a codelet  ...  This demand for flexible resource management is counter to the conventional wisdom about multi-core systems that has prevailed in recent years.  ...  A codelet is the unit of work scheduled for execution by a processing core of a multi-core computer system.  ... 
doi:10.1109/dfm.2014.18 fatcat:nzk6f4wslvcibapfwzaqolfkxe

An Improvement Over Threads Communications on Multi-Core Processors [article]

Reza Fotohi, Mehdi Effatparvar, Fateme Sarkohaki, Shahram Behzad, Jaber Hoseini balov
2019 arXiv   pre-print
misses in the destination's cache as well as reducing the coherence traffic on the bus. we show how we could improve the overall system performance by addition of these architecture optimizations to multi-core  ...  Multicore is an integrated circuit chip that uses two or more computational engines (cores) places in a single processor.  ...  Multi-core processors have become prevalent to address the growing demand for better performance. Recently, multi-core processors with three-level caches have been introduced to the market.  ... 
arXiv:1909.11644v2 fatcat:ajultuyzdfhujbmh373zq7bjhi

A Novel Process Mapping Strategy in Clustered Environments

Mohsen Soryani
2012 International Journal of Grid Computing & Applications  
The goal of this paper is to introduce a new process mapping strategy in multi-core clusters aimed at reducing network interface contention and improving inter-node communication performance of parallel  ...  Nowadays the number of available processing cores within computing nodes which are used in recent clustered environments, are growing up with a rapid rate.  ...  Pursuing this purpose, our goal in this paper, is to present a solution for mapping parallel processes to multi-core clusters so as to reduce network interface contention.  ... 
doi:10.5121/ijgca.2012.3204 fatcat:5vgyoqp47rdh7l5dd627e25yj4
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