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DCCB and SCC based fast circuit partition algorithm for parallel SPICE simulation
2009
2009 IEEE 8th International Conference on ASIC
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Circuit partition is required to these strategies, but traditional partition algorithms encounter difficulties when facing VLSI circuits for parallel simulation. ...
This paper presents an efficient circuit partition algorithm specially designed for VLSI circuit partition and parallel simulation. The algorithm is established on recognizing DCCB and SCC. ...
But most traditional methods may encounter difficulties in two aspects when facing VLSI partition problems for multi-core parallel simulation. ...
doi:10.1109/asicon.2009.5351211
fatcat:lfyr2xtzvzek5frsjzv3siufcq
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method
2007
Proceedings - Design Automation Conference
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for manufacturability. ♦ 3+ years C/C++ programming experience and 3+ years experience in Cadence and Synopsys tools. ...
. ♦ Advanced research experience in EDA technologies and methodologies that include VLSI physical layout design and logic synthesis, interconnect optimization, timing analysis, circuit integrated and design ...
(EDA) that includes studies in VLSI system design, layout optimization for robust VLSI circuit, algorithms for CAD, VLSI circuit design, circuit simulation and optimization and other core technologies ...
doi:10.1109/dac.2007.375280
fatcat:md6ijpfxa5hxfbuys5da6eovti
Fast capacitance extraction in multilayer, conformal and embedded dielectric using hybrid boundary element method
2007
Proceedings - Design Automation Conference
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for manufacturability. ♦ 3+ years C/C++ programming experience and 3+ years experience in Cadence and Synopsys tools. ...
. ♦ Advanced research experience in EDA technologies and methodologies that include VLSI physical layout design and logic synthesis, interconnect optimization, timing analysis, circuit integrated and design ...
(EDA) that includes studies in VLSI system design, layout optimization for robust VLSI circuit, algorithms for CAD, VLSI circuit design, circuit simulation and optimization and other core technologies ...
doi:10.1145/1278480.1278687
dblp:conf/dac/ZhouLS07
fatcat:ajwa26ykwza3xkv55r4s6hdnbq
Designing a Novel Ternary Multiplier Using CNTFET
2014
International Journal of Modern Education and Computer Science
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Carbon Nanotube Field Effect Transistors (CNTFET) are considered as good substitutes for Silicon Transistors (MOSFET). ...
Index Terms-CNTFET, Multi-valued logic (MVL), Multiplier, ternary logic, carbon nanotube. Designing a Novel Ternary Multiplier Using CNTFET ...
Since the length of the connections is indicated by the connections complex, it's obvious that using Multi Valued Logic (MVL) is very useful for implementing massive VLSI circuits. ...
doi:10.5815/ijmecs.2014.11.06
fatcat:nb4kiji5d5fj7dk56ewjulem6i
Design of Sigma Delta ADC for Bio Signal (ECG) Acquistion
2019
Zenodo
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In addition to compatibility with VLSI technology, sigma-delta converters provide high level of reliability and functionality and reduced chip cost. ...
The objective of this paper is to simulate and analyze the sigma-delta technology which proposed for the implementation in the low-digital-bandwidth voice communication. ...
Simulink is widely used in automatic control and digital signal processing for multi domain simulation and Model-Based Design. ...
doi:10.5281/zenodo.2566815
fatcat:fte773aaezd5hgmj3akqctpm2u
Systematic configuration and automatic tuning of neuromorphic systems
2011
2011 IEEE International Symposium of Circuits and Systems (ISCAS)
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Within this context, we present a framework we developed to simplify the configuration of multi-chip neuromorphic VLSI systems, and automate the mapping of neural network model parameters to neuromorphic ...
In order to implement complex event-based neuromorphic systems it is necessary to interface the neuromorphic VLSI sensors and devices among each other, to robotic platforms, and to workstations (e.g. for ...
The authors would like to thank the NCS group (http://ncs.ethz.ch/) for contributing to the development of the AER and multi-chip experimental setups. ...
doi:10.1109/iscas.2011.5937705
dblp:conf/iscas/SheikSNCI11
fatcat:umo2lfryzzdsxkbosjvvrcz4ra
GAP/D: VLSI Hardware for Parallel and Adaptive Distributed Genetic Algorithms
2009
2009 International Joint Conference on Computational Sciences and Optimization
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This paper presents GAP/D, a VLSI implementation of a dynamic adaptation scheme for the frequency of interdeme migration in distributed genetic algorithms (GA). ...
Distributed GA, or multi-deme-based GA, uses multiple populations which evolve concurrently. The purpose of dynamic adaptation is to improve convergence performance so as to obtain better solutions. ...
We carried out logic simulation and logic synthesis for preliminary evaluation of the design prior to actual VLSI fabrication. ...
doi:10.1109/cso.2009.454
dblp:conf/cso/KobayashiYN09
fatcat:2ovwzota3nb5njnti3jpjkvgz4
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
2017
IOSR Journal of VLSI and Signal processing
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LTspiceXVII is used as simulator to carry out the simulation work. ...
The layout was designed by use of an open source software namely Electric VLSI Design System which is Electronic Design Automation (EDA) tool. ...
GDI Technique allows improvements in design complexity level, transistor counts, static power dissipation and logic level swing. Fig.1 represents the basic building block of GDI cell. ...
doi:10.9790/4200-0702016773
fatcat:qdistkfybnglvo6tsn7uipnf3i
Modeling And Simulation Of Embryonic Hardware Structures Designed On FPGA-based Artificial Cell Network Topologies
2009
ECMS 2009 Proceedings edited by J. Otamendi, A. Bargiela, J. L. Montes, L. M. Doncel Pedrera
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These models are careful tested through computer-aided investigations, using a specially developed software toolkit designed for VLSI systems real-time simulation operations. I. ...
Own developed artificial cell model and artificial organism models are proposed, as basic components of a four level embryonic hardware structures. ...
The whole software simulation package is divided into three main components: the unit for the VLSI circuit's edition and modeling, the module for the real-time simulation, and more one unit for the graphical ...
doi:10.7148/2009-0613-0617
dblp:conf/ecms/SzaszCS09
fatcat:bo3ruzgzgneirdtoz6xcsjtjta
Design and Implementation of Vlsi Architecture for Arrhythmia Detection
2020
International journal of recent technology and engineering
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This projects presents a VLSI based design of high speed and minimum area for arrhythmia detection .It uses arithmetic distribution discrete wavelet transform for arrhythmia detection of QRS wave and is ...
When a person suffers from arrhythmic the heart may not pump sufficient blood to all body parts that is necessary for circulation. some of the symptoms of arrhythmia includes faintness ,fluttering your ...
The vlsi architecture is simulated using cadence is shown in figure 8 Figure 8: Simulation results of VLSI architecture
V. ...
doi:10.35940/ijrte.f8743.038620
fatcat:zbcm464xhvc6tk6ktujo2m64wm
Exploring olfactory sensory networks: Simulations and hardware emulation
2010
2010 Biomedical Circuits and Systems Conference (BioCAS)
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We present the results of a linear simulation, a spiking simulation with I&F neurons and a real-time hardware emulation using neuromorphic VLSI chips. ...
for real-time odor recognition. ...
The spiking simulation and VLSI emulation are perfectly suited for studying the temporal dynamics of the network. This work lies the foundation for future studies in this direction. ...
doi:10.1109/biocas.2010.5709623
fatcat:htmqgavbgvgzpgodsj3643uqqa
Adaptive Distributed Genetic Algorithms And Its Vlsi Design
2009
Zenodo
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This paper presents a dynamic adaptation scheme for the frequency of inter-deme migration in distributed genetic algorithms (GA), and its VLSI hardware design. ...
Through simulation experiments, we proved that our scheme achieves better performance than fixed frequency migration schemes. ...
We carried out logic simulation and logic synthesis for preliminary evaluation of the design prior to actual VLSI fabrication. ...
doi:10.5281/zenodo.1328805
fatcat:cdnar75dyzgxvnjloo6l32c2cq
Performance and Analysis of Voltage Scaled Repeaters for Multi-Walled Carbon Nanotubes as VLSI Interconnects
2014
International Journal of Computer Applications
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Multi-walled carbon nanotubes (MWCNT) are promising candidates for futuristic Nano-electronic applications. ...
In addition this paper deals with effect of voltage scaling in repeaters for long interconnects length in VLSI circuits in terms as propagation delay. ...
ITRS 2005 based simulation parameters The aspect ratio (A/R) for global level interconnects in ITRS is in the range of 2.5-2.8. For convenience, we have used aspect ratio (A/R) =3. ...
doi:10.5120/16235-5756
fatcat:6t2yqtzh45hmfdyzjgomnppnq4
VERY LARGE SCALE INTEGRATION TINY CHIP WITH NANOPOWER SENSOR APPLICATIONS
2012
International Journal of Electronics Signals and Systems
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Multi-die chip placement is done for fabrication. More advanced 0.35um CMOS process is used for low threshold voltage and enhanced supply voltage range. ...
Layout ,simulation and electrical characterization of the design were carried out by MENTOR GRAPHICS tool and CAD tools were used for the design Holding the scaling and process unchanged at 0.5μm as the ...
The trend is not only high-density and low-voltage, but also multi-level. ...
doi:10.47893/ijess.2012.1078
fatcat:rzabynfc3rbgppvsuqvixizmmu
A role for theorem proving in multi-processor design
[chapter]
1998
Lecture Notes in Computer Science
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high levels of expertise. ...
Indeed, simulation technology is still considered the most efficient verification technique for most parts of the designs, so ...
its ability to handle system-level (multiple-chip) complexity which often causes state explosion for model checking or infeasibly long simulation runs. ...
doi:10.1007/bfb0028730
fatcat:te2qpsnwfve3lk6jzn4n5v4k64
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