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The AXIOM project (Agile, eXtensible, fast I/O Module)

Dimitris Theodoropoulos, Dionisis Pnevmatikatos, Carlos Alvarez, Eduard Ayguade, Javier Bueno, Antonio Filgueras, Daniel Jimenez-Gonzalez, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernandez, David Oro (+4 others)
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
The AXIOM project (Agile, eXtensible, fast I/O Module) aims at researching new software/hardware architectures for the future Cyber-Physical Systems (CPSs).  ...  Our starting point uses power efficient multi-core nodes, such as ARM cores and FPGA accelerators on the same die, as in the Xilinx Zynq.  ...  ACKNOWLEDGMENT We thankfully acknowledge the support of the European Union H2020 program through the AXIOM project (grant ICT-01-2014 GA 645496), the Spanish Government, through the Severo Ochoa program  ... 
doi:10.1109/samos.2015.7363684 dblp:conf/samos/TheodoropoulosP15 fatcat:rhj5wzl6rzdwdn7nzbfk22sls4

Beyond block I/O

Michael Wei, John D. Davis, Ted Wobber, Mahesh Balakrishnan, Dahlia Malkhi
2013 Proceedings of the 6th International Systems and Storage Conference on - SYSTOR '13  
The basic block I/O interface used for interacting with storage devices hasn't changed much in 30 years.  ...  With the advent of very fast I/O devices based on solid-state memory, it becomes increasingly attractive to make many devices directly and concurrently available to many clients.  ...  Paul Barham helped us understand the performance of the system. And we especially thank Chuck Thacker and his team for building the Beehive system.  ... 
doi:10.1145/2485732.2485739 dblp:conf/systor/WeiDWBM13 fatcat:gsxbrkv3pjfk7pgkvbean5rqcq

The roles of FPGAs in reprogrammable systems

S. Hauck
1998 Proceedings of the IEEE  
This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems.  ...  In this paper, we discuss the promise and problems of reprogrammable systems.  ...  Because the packaging technology necessary for such high I/O chips is somewhat exotic, however, high-I/O FPIC's can be expensive.  ... 
doi:10.1109/5.663540 fatcat:rrpdgyfqyzdcxdcplblk6gv42a

A practical FPGA-based framework for novel CMP research

Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Tesylar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
2007 Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07  
ATLAS uses the BEE2 multi-FPGA board to provide a system with 8 PowerPC cores that run at 100MHz and runs Linux.  ...  Specifically, we address issues such as overall performance, challenges of mapping ASIC-style CMP RTL on to FPGAs, software support, the selection criteria for the base processor, and the challenges of  ...  The design has been mapped onto the BEE2 multi-FPGA board shown in Figure 2 [16] .  ... 
doi:10.1145/1216919.1216936 dblp:conf/fpga/WeeCNTGKO07 fatcat:qamfrw43zngcvmcjcr3xsxfvwq

A distributed I/O low-level controller for highly-dexterous snake robots

Paul Thienphrapa, Peter Kazanzides
2008 2008 IEEE Biomedical Circuits and Systems Conference  
distribute I/O and centralize processing.  ...  Motivated by dexterous snake-like robots for minimally invasive surgery, this paper explores the use of IEEE 1394 (FireWire), attached directly to low-latency field-programmable gate arrays (FPGAs), to  ...  (Coeur d'Alene, Idaho) and Fran Wu for their extensive help with the design and layout of the controller boards, and Mitch Williams for his help with software setup.  ... 
doi:10.1109/biocas.2008.4696861 fatcat:yhm6sapcz5gyvgeovflcxzkmki

A methodology for the design and deployment of reliable systems on heterogeneous platforms

Hugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans
2012 2012 International Conference on Reconfigurable Computing and FPGAs  
Heterogeneous multi-target platforms composed of processors, FPGAs, and specialized I/O are popular targets for embedded applications.  ...  However, prior design approaches do not sufficiently characterize these non-functional requirements in the application or in the mapping on the multitarget platform.  ...  To control the life cycle of the task on a FPGA I/O board we use the LabVIEW FPGA Host Fig. 9 . 9 LV Host Front Panel for Pattern 1 Fig. 10 . 10 LV FPGA DMR Block Diagram for Pattern 2 Fig. 11 .  ... 
doi:10.1109/reconfig.2012.6416722 dblp:conf/reconfig/AndradeGRE12 fatcat:cerxwbi6ebd5hibb2fhezk5zii

Deployment and future prospects of high performance diagnostics featuring serial I/O (SIO) data acquisition (DAQ) at ASDEX Upgrade

K. Behler, H. Blank, H. Eixenberger, M. Fitzek, A. Lohs, K. Lüddecke, R. Merkel
2012 Fusion engineering and design  
This paper presents results achieved and experiences gained in the deployment of SIO I, the status of SIO II development (currently in the prototype phase), and projected enhancements and updates to existing  ...  An effort has been started to develop a SIO version 2 (SIO II) featuring upgraded serial links and a more powerful FPGA for merging and forwarding data streams to host computer memory.  ...  We also would like to thank Constantin Gonzales from Oracle (former SUN Microsystems) who spent a day with us breeding over Solaris performance issues and how to unleash the power of dtrace for our investigations  ... 
doi:10.1016/j.fusengdes.2012.09.020 fatcat:tbneqtywsbg2bici5ghfvr6jh4

The Triptych FPGA architecture

G. Borriello, C. Ebeling, S.A. Hauck, S. Burns
1995 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.  ...  This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits.  ...  Acknowledgments Thanks to Christopher Hébert and the other students of CSE568, Winter quarter 1991 for contributing to the early design phases of the Triptych layout.  ... 
doi:10.1109/92.475968 fatcat:m46uitx26nbihfe6bt3nkibh2q

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs

Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08  
To overcome this bottleneck, we propose the PROTOFLEX simulation architecture, which uses FPGAs to accelerate simulation.  ...  Prior FPGA approaches that prototype a complete system in hardware are either too complex when scaling to large-scale configurations or require significant effort to provide full-system support.  ...  Funding for this work was provided in part by grants from the C2S2 Marco Center, NSF CCR-509356, and an IBM Faculty Award. We thank Xilinx for their generous FPGA and tool donations.  ... 
doi:10.1145/1344671.1344684 dblp:conf/fpga/ChungNHFM08 fatcat:mbor5pikwzgczl77255jguqnuq

On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations [article]

Michael Schaffner, Luca Benini
2018 arXiv   pre-print
With this report, we aim at clarifying this issue by comparing measured application performance on GPU-dense compute nodes with performance and cost estimates of a FPGA-based single- node system.  ...  However, we also note that scaled multi-node systems could potentially benefit from a hybrid composition, where GPUs are used for compute intensive parts and FPGAs for latency and communication sensitive  ...  Further, they transfer many parameters that could be shared among several particles on a per atom basis onto the the accelerator which leads to significant I/O overhead.  ... 
arXiv:1808.04201v1 fatcat:yzos5gym5ndojoooesfsmw2iwq

A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only)

Ehsan Ghasemi, Paul Chow
2016 Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16  
We prototype our framework within the Apache Spark analytics tool running on a CPU-FPGA heterogeneous cluster.  ...  As a specific application case study, we have chosen the MapReduce paradigm to implement a multi-purpose, scalable, and customizable RTL accelerator inside the FPGA, capable of incorporating custom High-Level  ...  The limited disk I/O transfer rate inflicts a huge bottleneck on the overall performance.  ... 
doi:10.1145/2847263.2847294 dblp:conf/fpga/GhasemiC16 fatcat:7e7ezyt7rfdjpgkwhxzvricbly

Accessible near-storage computing with FPGAs

Robert Schmid, Max Plauth, Lukas Wenzel, Felix Eberhardt, Andreas Polze
2020 Proceedings of the Fifteenth European Conference on Computer Systems  
We introduce the Metal FS framework to improve the accessibility of FPGA-based near-storage accelerators: Firstly, we present a near-storage-compute-aware file system that enables self-contained, reusable  ...  Secondly, we provide an integrated build process for FPGA overlay images that starts with the acquisition of compute kernels through a package manager and finally allows to dynamically configure near-storage  ...  Acknowledgements We thank the anonymous reviewers and our shepherd, Tim Harris, for their valuable feedback.  ... 
doi:10.1145/3342195.3387557 dblp:conf/eurosys/SchmidPWEP20 fatcat:ykijhsup6jdpnkpcer2picfbfu

Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud

Kemal Ebcioglu, Ismail San
2022 ACM Transactions on Reconfigurable Technology and Systems  
Invoking the multi-chip accelerator is functionally identical to invoking the single-threaded sequential code the multi-chip accelerator is compiled from.  ...  Therefore, software development for using the multi-chip accelerator hardware is simplified, but the multi-chip accelerator can exhibit extremely high parallelism.  ...  The authors believe that sequential code can ofer a more productive way to design future multi-chip FPGA-based or ASIC-based application-speciic hardware accelerator systems.  ... 
doi:10.1145/3507698 fatcat:tizeillzrjhshngssrbtdunegm

Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation

Chen-Han Hoy, Venkatraman Govindarajuz, Tony Nowatzki, Ranjini Nagaraju, Zachary Marzec, Preeti Agarwal, Chris Frericks, Ryan Cofell, Karthikeyan Sankaralingam
2015 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA  ...  Through the prototype, this paper evaluates the fundamental principles of DySER acceleration.  ...  ACKNOWLEDGMENTS Support for this research was provided by NSF under the following grants: CCF-0845751, CCF-0917238, and CNS-0917213.  ... 
doi:10.1109/ispass.2015.7095806 dblp:conf/ispass/HoGNNMAFCS15 fatcat:k7lf47oavveqfiytf4qnk75j2e

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
The speculative functional model enables the simulator to be parallelized, implementing the timing model in FPGA hardware for speed and the functional model using a modified full-system simulators.  ...  This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (iii) model the entire  ...  We would like to thank Joel Emer of Intel for helpful discussions and assistance in integrating FAST into AWB, Paul Hartke of Xilinx for his help with everything FPGAs and Michael Monkang Chu of DRC Computer  ... 
doi:10.1109/micro.2007.4408260 fatcat:z2syt5x7i5fbfh5xnsocklbt6y
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