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doppioDB
2017
Proceedings of the 2017 ACM International Conference on Management of Data - SIGMOD '17
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Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., matching regular expressions) or the data is less structured (e.g., text or long strings). In this demonstration we show the benefit of using specialized hardware for such tasks and highlight the importance of a flexible, reusable mechanism for extending database engines with hardware-based
doi:10.1145/3035918.3058746
dblp:conf/sigmod/SidlerIOKA17
fatcat:7w66bubd2zeapamrlluwr2vodq
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... ators. We present doppioDB which consists of MonetDB, a mainmemory column store, extended with Hardware User Defined Functions (HUDFs). In our demonstration the HUDFs are used to provide seamless acceleration of two string operators, LIKE and REGEXP_LIKE, and two analytics operators, SKYLINE and SGD (stochastic gradient descent). We evaluate doppioDB on an emerging hybrid multicore architecture, the Intel Xeon+FPGA platform, where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can directly access the database tables. For integration we rely on HUDFs as a unit of scheduling and management on the FPGA. In the demonstration we show the acceleration benefits of hardware operators, as well as their flexibility in accommodating changing workloads.
doppioDB 1.0: Machine Learning inside a Relational Engine
2019
IEEE Data Engineering Bulletin
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The work of Owaida et al. [23, 24] proposes an accelerator that is parameterizable at runtime to support different tree models. ...
dblp:journals/debu/AlonsoIKOS19
fatcat:6vxbetufyrddxpy7tidsltuov4
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver
[chapter]
2017
Advanced Logic Synthesis
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We present an algorithm that progressively generates canonical irredundant Sums Of Products (SOPs) for completely-and incompletely-specified Boolean functions using a satisfiability (SAT) solver. The progressive generation allows for real time monitoring and early termination, as well as for generation of partial SOPs for incremental applications. On the other hand, canonicity brings independence of the original representation and often yields smaller and more regular SOPs that lead to smaller
doi:10.1007/978-3-319-67295-3_8
fatcat:alrawfwgqfdgresrpwk624lmme
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... ircuits after algebraic factoring. Also, canonicity is key in applications such as constraint solving and random assignment generation, which traditionally rely on methods based on Binary Decision Diagram (BDD). However, in contrast with BDDs, our algorithm can relax canonicity to improve speed and scalability. In general, our method is more scalable for benchmarks with many structurally isomorphic outputs. It also improves the quality of results up to 10%, in terms of the SOP size, compared to a state-of-the-art BDD-based method. Experiments with global circuit restructuring using SAT-based SOPs show that area-delay product can be improved up to 27%, compared to global restructuring using BDD-based SOPs.
Accelerating Pattern Matching Queries in Hybrid CPU-FPGA Architectures
2017
Proceedings of the 2017 ACM International Conference on Management of Data - SIGMOD '17
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Taking advantage of recently released hybrid multicore architectures, such as the Intel Xeon+FPGA machine, where the FPGA has coherent access to the main memory through the QPI bus, we explore the benefits of specializing operators to hardware. We focus on two commonly used SQL operators for strings: LIKE, and REGEXP_LIKE, and provide a novel and efficient implementation of these operators in reconfigurable hardware. We integrate the hardware accelerator into MonetDB, a main-memory column
doi:10.1145/3035918.3035954
dblp:conf/sigmod/SidlerIOA17
fatcat:7jx3pejeu5gszk37scfweyypxa
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... and demonstrate a significant improvement in response time and throughput. Our Hardware User Defined Function (HUDF) can speed up complex pattern matching by an order of magnitude in comparison to the database running on a 10-core CPU. The insights gained from integrating hardware based string operators into MonetDB should also be useful for future designs combining hardware specialization and databases.
Is advance knowledge of flow sizes a plausible assumption?
2019
Symposium on Networked Systems Design and Implementation
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Recent research has proposed several packet, flow, and coflow scheduling methods that could substantially improve data center network performance. Most of this work assumes advance knowledge of flow sizes. However, the lack of a clear path to obtaining such knowledge has also prompted some work on non-clairvoyant scheduling, albeit with more limited performance benefits. We thus investigate whether flow sizes can be known in advance in practice, using both simple heuristics and learning
dblp:conf/nsdi/DukicJKOZS19
fatcat:4an4gyssbbb4nh2cfh7fhoxmke
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... Our systematic and substantial efforts for estimating flow sizes indicate, unfortunately, that such knowledge is likely hard to obtain with high confidence across many settings of practical interest. Nevertheless, our prognosis is ultimately more positive: even simple heuristics can help estimate flow sizes for many flows, and this partial knowledge has utility in scheduling. These results indicate that a presumed lack of advance knowledge of flow sizes is not necessarily prohibitive for highly efficient scheduling, and suggest further exploration in two directions: (a) scheduling under partial knowledge; and (b) evaluating the practical payoff and expense of obtaining more knowledge.
Single-Pass Covariance Matrix Calculation on a Hybrid FPGA/CPU Platform
2020
EPJ Web of Conferences
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Covariance matrices are used for a wide range of applications in particle physics, including Kálmán filter for tracking purposes or Primary Component Analysis for dimensionality reduction. Based on a novel decomposition of the covariance matrix, a design that requires only one pass of data for calculating the covariance matrix is presented. Two computation engines are used depending on parallelizability of the necessary computation steps. The design is implemented onto a hybrid FPGA/CPU system
doi:10.1051/epjconf/202024509006
fatcat:jpf6q6yydje4vdggjtbx2qpn3e
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... nd yields speed-up of up to 5 orders of magnitude compared to previous FPGA implementation.
Lowering the latency of data processing pipelines through FPGA based hardware acceleration
2019
Proceedings of the VLDB Endowment
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Part of the work of Muhsen Owaida was funded by a grant from Amadeus. Figure 1 : 1 An Example of a Decision Tree. Nodes 0 -2 are decision nodes and nodes 3 -6 are leaf nodes. ...
doi:10.14778/3357377.3357383
fatcat:xfngr7mstjawjibykyhpzbizce
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms
2014
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
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The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the architectural innovations that ultimately benefit applications. To address this challenge, we need benchmarks that capture the execution patterns (i.e., dwarfs or motifs) of applications, both present and future, in order to guide future hardware design. Furthermore, we desire a
doi:10.1109/asap.2014.6868650
dblp:conf/asap/KrommydasFOAB14
fatcat:2jiwfdlfgjakroxde2n37y734y
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... common programming model for the benchmarks that facilitates code portability across a wide variety of different processors (e.g., CPU, APU, GPU, FPGA, DSP) and computing environments (e.g., embedded, mobile, desktop, server). As such, we present the latest release of OpenDwarfs, a benchmark suite that currently realizes the Berkeley dwarfs in OpenCL, a vendor-agnostic and open-standard computing language for parallel computing. Using OpenDwarfs, we characterize a diverse set of fixed and reconfigurable parallel platforms: multicore CPUs, discrete and integrated GPUs, Intel Xeon Phi coprocessor, as well as a FPGA. We describe the computation and communication patterns exposed by a representative set of dwarfs, obtain relevant profiling data and execution information, and draw conclusions that highlight the complex interplay between dwarfs' patterns and the underlying hardware architecture of modern parallel platforms.
ASAP 2014 program
2014
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
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Secure Interrupts
on low-end microcontrollers
12:50 -14:20 Lunch Break
14:20 -15:30 Session 5: Programming
Regular Papers:
72
Konstantinos Krommydas, Wu-Chun Feng, Muhsen Owaida, Christos D. ...
doi:10.1109/asap.2014.6868622
fatcat:qhye3xi6yzaoxfngx3ta64t4ku
Table of contents
2014
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
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Owaida, Christos D. ...
Piessens, Dries Schellekens, Ingrid Verbauwhede)
[Search]
Regular Papers
153
On the Characterization of OpenCL Dwarfs on Fixed and Reconfigurable Platforms
(Konstantinos Krommydas, Wu-chun Feng, Muhsen ...
doi:10.1109/asap.2014.6868611
fatcat:7bu4iqnpebaslcsnd4lwtcfcei
Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges
[article]
2017
arXiv
pre-print
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Focus on how to integrate an FPGA accelerator into a database engine from the system architecture level, Muhsen Owaida et al. ...
Muhsen Owaidad et al. propose a framework, Centaur [32] running on an FPGA. ...
arXiv:1712.04771v1
fatcat:3lxv45qb4zaqpagtn3eghrmroe
TCUDB: Accelerating Database with Tensor Processors
[article]
2021
arXiv
pre-print
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In 2016 IEEE
[66] Muhsen Owaida, Gustavo Alonso, Laura Fogliarini, Anthony Hock-Koon, and International Conference on Big Data (Big Data). 273–283.
Pierre-Etienne Melet. 2019. ...
arXiv:2112.07552v1
fatcat:y6furfuc7nh5jml3cew7mqngry