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Parallelized radix-4 scalable montgomery multipliers

Nathaniel Ross Pinckney, David Money Harris
2007 Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07  
The design does not require hardware multipliers, and uses parallelized multiplication to shorten the critical path.  ...  This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation.  ...  required for Montgomery multiplication decreases linearly with amount of hardware in the multiplier.  ... 
doi:10.1145/1284480.1284562 dblp:conf/sbcci/PinckneyH07 fatcat:wbjirxbcfjazjbxjl6ve66t3xq

A Black Hen Lays White Eggs [chapter]

Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume
2008 Lecture Notes in Computer Science  
In an attempt to extend the lifespan of such multipliers, double-size techniques compute modular multiplications with twice the bit-length of the multipliers.  ...  Techniques are known for extending the bit-length of classical Euclidean multipliers, of Montgomery multipliers and the combination thereof, namely bipartite multipliers.  ...  The problem has motivated double-size techniques to compute modular multiplication with twice the bit length of hardware multipliers. Yoshino et al.'  ... 
doi:10.1007/978-3-540-85893-5_6 fatcat:sebcbbdfmnetnheue6zaccktqe

Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath

Johann Großschädl, Erkay Savas, Kazim Yumbul
2009 2009 International Conference on Reconfigurable Computing and FPGAs  
Our idea is to extend the datapath of a Montgomery multiplier in such a way that it can also perform an ordinary multiplication of two n-bit operands (without modular reduction), yielding a 2n-bit result  ...  We show that performing a 2n-bit modular multiplication on an n-bit multiplier can be done in 5n clock cycles, whereby we assume that the n-bit modular multiplication takes n cycles.  ...  When dimensioned for a precision of n bits, our multiplier executes a Montgomery modular multiplication with operands of length (at most) n bits "directly" in circa n clock cycles.  ... 
doi:10.1109/reconfig.2009.83 dblp:conf/reconfig/GrossschadlSY09 fatcat:rqhhpoviz5d7rlf6majkmx3vmm

Hardware modules of the RSA algorithm

Velibor Skobic, Branko Dokic, Zeljko Ivanovic
2014 Serbian Journal of Electrical Engineering  
The modules are analyzed for different key lengths (16 to 1024) in terms of the number of logic elements, the maximum frequency and speed.  ...  The RSA algorithm is implemented on FPGA integrated circuit EP4CE115F29C7, family Cyclone IV, Altera. Four modules of Montgomery algorithm are designed using VHDL.  ...  Selected FPGA device allows key lengths of 16, 32, 64, 128, 256, 512 and 1024 bits. Number of required logic elements increases with the key length.  ... 
doi:10.2298/sjee140114011s fatcat:lw24ckzhjbdldjhbekhnvuje3u

A New Modified CMM Modular Exponentiation Algorithm

Abdalhossein Rezai, Parviz Keshavarzi
2011 International Journal of Intelligent Computing Research  
This paper presents a new modified Montgomery modular multiplication algorithm based on multiple bit scan-multiple bit shift technique, sliding window method and signed-digit representation.  ...  In this new algorithm, the common part of modular multiplication is computed once rather than several times. So the security of the cryptosystem which used this new algorithm increased considerably.  ...  In the each iteration of multiplication phase of algorithm 6, l i bits of multiplier and n-bit multiplicand are processed.  ... 
doi:10.20533/ijicr.2042.4655.2011.0021 fatcat:opmihtwvcrcczamm64cggqszg4

Montgomery Multiplication Using Vector Instructions [chapter]

Joppe W. Bos, Peter L. Montgomery, Daniel Shumow, Gregory M. Zaverucha
2014 Lecture Notes in Computer Science  
When instantiating modular exponentiation with this parallel version of Montgomery multiplication we observed a performance increase of more than a factor of 1.5 compared to the sequential implementation  ...  in OpenSSL for the classical arithmetic logic unit on the Atom platform for 2048-bit moduli.  ...  Also, we thank the anonymous reviewers of SAC for their helpful feedback and thank Daniel J. Bernstein and Tanja Lange for the additional suggestions, both of which improved the quality of this paper.  ... 
doi:10.1007/978-3-662-43414-7_24 fatcat:xl677jumtvejtg6x2mldra7lrm

Modular exponent realization on FPGAs [chapter]

Jüri PÕldre, Kalle TammemÄe, Marek Mandre
1998 Lecture Notes in Computer Science  
The partitioning of calculations is analyzed with respect to interconnect signal numbers and added delay.  ...  The partitioned blocks are used for implementation approximations of two different multiplier architectures. Examples are provided for 3 families of FPGAs: XC4000, XC6200 and FLEX10k  ...  This reduces the length of operands and thus hardware consumption. The algorithms rank k is the amount of bits handled at one step.  ... 
doi:10.1007/bfb0055261 fatcat:ncqz4q2d2jcm5dohud2g2dzb4a

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

jiakun li, shunran zhong, zhe li, shan cao, jingqi zhang, Weijiang Wang
2019 IEEE Access  
Since the multiplier and its segments work in different bit-length and refer to different fields, the proposed architecture can also be upgraded to a reconfigurable design to support multiple-field point  ...  A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication.  ...  GF(2 m ) with the longest and the shortest bit length of m.  ... 
doi:10.1109/access.2019.2903170 fatcat:7bvvfu45kzgipmmaha7irnhxh4

Bipartite Modular Multiplication [chapter]

Marcelo E. Kaihara, Naofumi Takagi
2005 Lecture Notes in Computer Science  
The upper part and the lower part of the multiplier are processed using the interleaved modular multiplication algorithm and the Montgomery algorithm respectively.  ...  Conversions back and forth between the original integer set and the new residue system can be performed at speeds up to twice that of the Montgomery method without the need for precomputed constants.  ...  Acknowledgments The authors would like to thank Associate Professor Kazuyoshi Takagi for his valuable comments and discussions and to Miss Grith Christensen for her help in preparing this paper.  ... 
doi:10.1007/11545262_15 fatcat:lt5u2kh225gwvmvtyy7pjyv5ui

A compact FPGA-based montgomery modular multiplier

Ahmed A. H. Abd-elkader, Mostafa Rashdan, El-Sayed A. M. Hasaneen, Hesham F. A. Hamed
2021 Indonesian Journal of Electrical Engineering and Computer Science  
<span>This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM).  ...  The proposed design is a modification in the structure of MMM without any multiplication or subtraction processes.  ...  Therefore, a cryptographic system with high performance depends on the construction of modular multiplication. A Montgomery modular multiplier (MMM) is the widely used modular multiplier [3] .  ... 
doi:10.11591/ijeecs.v21.i2.pp735-743 fatcat:mfdk6akdsfaz3fpetttgpvgk7m

Achieving NTRU with montgomery multiplication

C. O'Rourke, B. Sunar
2003 IEEE transactions on computers  
In this paper, we propose a new unified architecture that utilizes the Montgomery Multiplication algorithm to perform a modular multiplication for both integers and binary polynomials and NTRU's polynomial  ...  Furthermore, the architecture is highly efficient in terms of area and speed.  ...  ACKNOWLEDGMENTS The authors thank Gunnar Gaubatz for his contributions to the unified Montgomery Multiplier core design.  ... 
doi:10.1109/tc.2003.1190585 fatcat:kuybatdgfbg3jjfr6hndvaiwma

Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems [chapter]

Lejla Batina, Geeke Bruin-Muurling, Sıddıka Berna Örs
2004 Lecture Notes in Computer Science  
In latter option it can include a few dedicated large number arithmetic units each of which is a systolic array performing the Montgomery Modular Multiplication (MMM).  ...  The bound on the Montgomery parameter has been optimized to facilitate more secure ECC point operations.  ...  Because the critical path of the systolic array is the same as the critical path of one PC, the clock frequency of the Montgomery multiplier will be the same for all bit-lengths.  ... 
doi:10.1007/978-3-540-24660-2_20 fatcat:6a73zujjwfdhnltdc4bmkkkz3q

An FPGA implementation of an elliptic curve processor GF(2m)

Nele Mentens, Siddika Berna Ors, Bart Preneel
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length  ...  This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public  ...  Montgomery modular multiplication circuit (MMMC) (4.1) The bit length m, the word length w and the key length l are input parameters to the circuit.  ... 
doi:10.1145/988952.989062 dblp:conf/glvlsi/MentensOP04 fatcat:cugujgsa5vhk3n4sbvfopogsym

Efficient prime-field arithmetic for elliptic curve cryptography on wireless sensor nodes

Yang Zhang, J. Grossschadl
2011 Proceedings of 2011 International Conference on Computer Science and Network Technology  
We describe an optimized variant of Montgomery multiplication, based on Gura et al's hybrid technique, that takes the low weight of such primes into account to minimize execution time.  ...  Our implementation for the ATmega128 is able to perform a multiplication in a 160-bit OPF in 3,542 clock cycles, which represents a new speed record for 160-bit modular multiplication on an 8-bit processor  ...  cost scales linearly with the operand length.  ... 
doi:10.1109/iccsnt.2011.6181997 fatcat:54zono7kb5dmrc2mdnlyxbetce

A scalable dual mode arithmetic unit for public key cryptosystems

F. Crowe, A. Daly, W. Marnane
2005 International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II  
A hardware optimised version of the Montgomery algorithm is employed to perform modular multiplication efficiently.  ...  At current security levels of 80 bits, the corresponding key sizes for ECC and RSA vary between 160 and 1,024 bits respectively.  ...  The architecture is designed in a generic way with the bit length and number of processors as parameters.  ... 
doi:10.1109/itcc.2005.33 dblp:conf/itcc/CroweDM05 fatcat:obu54n3un5a43nf7z2xke4l3cu
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