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Moguls
2011
SIGARCH Computer Architecture News
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To facilitate architects to quickly explore the design space of memory hierarchies, we propose an analytical performance model called Moguls. ...
The Moguls model estimates the performance of an application on a system, using the bandwidth demand of the application for a range of cache capacities and the bandwidth provided by the system with those ...
To help computer architects quickly explore the design space for memory hierarchies to improve bandwidth, this paper makes the following contributions. • An analytical model called Moguls is proposed to ...
doi:10.1145/2024723.2000109
fatcat:yewnfmgm2nbrnmqtdgtlckh5ru
Moguls
2011
Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11
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To facilitate architects to quickly explore the design space of memory hierarchies, we propose an analytical performance model called Moguls. ...
The Moguls model estimates the performance of an application on a system, using the bandwidth demand of the application for a range of cache capacities and the bandwidth provided by the system with those ...
To help computer architects quickly explore the design space for memory hierarchies to improve bandwidth, this paper makes the following contributions. • An analytical model called Moguls is proposed to ...
doi:10.1145/2000064.2000109
dblp:conf/isca/SunHKZXXC11
fatcat:fd2xml6de5czzhjuebzx73op3a
Condor
2015
Proceedings of the 2015 ACM Conference on Special Interest Group on Data Communication - SIGCOMM '15
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Network architects must trade off many criteria to design costeffective, reliable, and maintainable networks, and typically cannot explore much of the design space. ...
The design space for large, multipath datacenter networks is large and complex, and no one design fits all purposes. ...
We also thank Christopher Hodsdon, Tom Anderson and Vincent Liu, our shepherd Aditya Akella, and the SIGCOMM reviewers. ...
doi:10.1145/2785956.2787476
dblp:conf/sigcomm/SchlinkerMSMVYK15
fatcat:nvvyjsvbkneljc7ue73dmqr5xq
Experiences with Modeling Network Topologies at Multiple Levels of Abstraction
2020
Symposium on Networked Systems Design and Implementation
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We also describe the software base that supports efficient use of MALT, as well as numerous, sometimes painful lessons we have learned about curating the taxonomy for a comprehensive, and evolving, representation ...
MALT provides interoperability across our network-management software, and its support for abstraction allows us to explicitly tie low-level network elements to high-level design intent. ...
Acknowledgements Hundreds (at least) of our colleagues have contributed code, models, queries, documents, and sometimes painful experience to the MALT journey, and continue to do so; we cannot possibly ...
dblp:conf/nsdi/MogulGPSTKZ20
fatcat:7xxp25akdnc57b75gbzrvf3wwu
Network locality at the scale of processes
1991
Proceedings of the conference on Communications architecture & protocols - SIGCOMM '91
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Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals. ...
Observations of typical LANs show high perprocess locality; that is, packets to a host usually arrive for the process that most recently sent a packet, and often with little intervening delay. ...
One would expect latencies to drop considerably for a faster network than Ethernet, especially for networks such as Autonet [36] where the aggregate bandwidth is greater than the link bandwidths. ...
doi:10.1145/115992.116017
dblp:conf/sigcomm/Mogul91
fatcat:siv73cfyrjhnpam5eul2iicgdu
Visa protocols for controlling interorganizational datagram flow
1989
IEEE Journal on Selected Areas in Communications
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Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals. ...
One method for doing so is the use of visas, a cryptographic technique for authenticating and authorizing a flow of datagrams. ...
One approach is to introduce controls at a number of levels in the protocol hierarchy. ...
doi:10.1109/49.17712
fatcat:rptgnisd5fdkfdvvibz2r7fmli
Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies
2012
Proceedings of the 9th conference on Computing Frontiers - CF '12
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We use the model to explore the cache hierarchy design space and present latency-power tradeoffs for memory intensive SPEC benchmarks and scientific applications. ...
The results indicate that a flattened hierarchy lowers power and improves average memory access time. ...
Moguls [26] is another memory model that considers bandwidth and power (only dynamic power) in designing a memory hierarchy. ...
doi:10.1145/2212908.2212923
dblp:conf/cf/YoonGRS12
fatcat:aydwzcyjmrdtvdvdeggupxkoqm
The influence of ATM on operating systems
2002
Computer communication review
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These created considerable challenges for the O.S. designer, since a small protocol data unit size (the 48 byte "cell") and link bandwidths within a (binary) order of magnitude of memory bandwidths demanded ...
The features of ATM offered many attractions to the application community, such as fine-grained multiplexing and high-throughput links. ...
bandwidth, and the Model 580 to have 2.5 Gbit/s of memory bandwidth). ...
doi:10.1145/774749.774755
fatcat:fdkfviwvqbez5ifj3ryunzolca
Cache restoration for highly partitioned virtualized systems
2012
IEEE International Symposium on High-Performance Comp Architecture
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Through cycle-accurate simulation of a POWER7 system, we show that when applied to its private per-core L3 last-level cache, the warm cache translates into 20% on average performance improvement for a ...
time-sharing, down to a percentage of a core being allotted to a virtual machine. ...
In future work, we plan to explore cache restoration for these structures as well, in addition to improved mechanisms for reducing prefetch bandwidth without sacrificing coverage. ...
doi:10.1109/hpca.2012.6169029
dblp:conf/hpca/DalyC12
fatcat:oj3lparhifffnmfytdnhdbwjbu
Thin-client Web access patterns: Measurements from a cache-busting proxy
2002
Computer Communications
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We present the aggregate browser cache success function (hit rate vs. cache size) of the entire client population and discuss design implications for memory-and bandwidth-constrained Web clients. ...
This paper describes a new technique for measuring Web client request patterns and analyzes a large client trace collected using the new method. ...
Acknowledgements Literally dozens of WebTV personnel helped to collect the anonymized trace described in this paper. My manager, Stuart Ozer, lent resources and his expertise to the project. ...
doi:10.1016/s0140-3664(01)00407-8
fatcat:rtntweveqbhmde42eednsmsv2q
Power-efficient networking for balanced system designs
2011
Proceedings of the 4th Workshop on Power-Aware Computing and Systems - HotPower '11
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However, in a balanced system design, these changes call for matching improvement in the network subsystem as well. ...
In this paper, we evaluate the benefits of using an alternative, high-bandwidth, low-power, interconnect-PCIe-for power-efficient networking. ...
, Moray McLaren and Jeff Mogul as well as valuable reviewer comments. ...
doi:10.1145/2039252.2039255
fatcat:jogavl54yncsrdcowhoopdo5tq
Andromeda: Performance, Isolation, and Velocity at Scale in Cloud Network Virtualization
2018
Symposium on Networked Systems Design and Implementation
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https://www.usenix.org/conference/nsdi18/presentation/dalton This paper is included in the Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI '18). ...
Acknowledgements We would like to thank our reviewers, shepherd Michael Kaminsky, Jeff Mogul, Rama Govindaraju, Aspi Siganporia, and Parthasarathy Ranganathan for paper feedback and guidance. ...
We also thank the following individuals, who were instrumental in the success of the project: Aspi Siganporia, Alok Kumar, Andres Lagar-Cavilla, Bill Sommerfeld, Carlo Contavalli, Frank Swiderski, Jerry ...
dblp:conf/nsdi/DaltonSAAGFRZRD18
fatcat:ebhgpc6dbzawfg2opnn2rcufcm
Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory
2013
ACM Transactions on Architecture and Code Optimization (TACO)
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Limited PCM write bandwidth is a critical obstacle to achieve good performance from hybrid DRAM/PCM memory systems. ...
To reduce the number of PCM writes, we propose a DRAM cache organization that employs compression. A new delta compression technique for modified data is used to achieve a large compression ratio. ...
We model an 8-core 2GHz CMP with in-order cores and a cache hierarchy similar to the IBM Power7 [Sinharoy et al. 2011 ] with a 32MB L3 cache. ...
doi:10.1145/2400682.2400714
fatcat:hzxwewhl6zgjxitffjdi3ygtpq
Digest of proceedings seventh IEEE workshop on hot topics in operating systems March 29-30 1999, Rio Rico, AZ
1999
ACM SIGOPS Operating Systems Review
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This paper argues that system designers should treat reliability as a property that induces a hierarchy of levels in a system, much as access time induces a memory hierarchy. ...
He added that he did expect partitioned context models to offer a substantial performance improvement over last successor models, since they are able to eliminate nearly a third of the misses sustained ...
doi:10.1145/334598.334600
fatcat:pm3qjay64vcunc7skvjeodzwsu
AVid: Annotation driven video decoding for hybrid memories
2012
2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia
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Adopting emerging non-volatile memory (NVM) technologies is a viable solution to minimize the increasing memory leakage power in today's embedded systems. ...
However, in order to take advantage of the many benefits in NVMs, software must account for their high write overheads. ...
Compared to previous video codecs it has a reduction of 50% in bandwidth requirements for a given image quality [27] . ...
doi:10.1109/estimedia.2012.6507022
dblp:conf/estimedia/StancuBDN12
fatcat:aonhl7fsgvao3mlirdrz2wtwne
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