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Area and Power Efficient Self-Checking Modulo 2^n +1 Multiplier

B. Mounika, Sangeeta Singh
2013 International Journal of Computer Applications  
In this paper, a new circuit implementation of an area and power efficient self-checking modulo 2 n +1 multiplier based on residue codes are proposed.  ...  The proposed self-checking modulo multipliers for various values of input are specified in Verilog Hardware Description Language (HDL), simulated by using XILINX ISE and synthesized using cadence RTL encounter  ...  The second architecture is realized by using modulo 2 n +1 adder, which consists of a carry-save adder and a final carry-select addition unit to reduce design complexity [2] .  ... 
doi:10.5120/13243-0693 fatcat:2yu3lsx7andahlg5zbr5zhmewu

A CAD framework for generating self-checking multipliers based on residue codes

I. Alzaher Noufal, M. Nicolaidis
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
However, parity prediction self-checking multipliers involve a hardware overhead significantly higher than for other blocks.  ...  basic data path blocks such as, adders, ALUs, shifters, register files, etc.  ...  Sklansky 3 3 3 3 Carry Lookahed Units 3 3 3 3 Table 1 : 1 Check bases found for different structures of fast carry determination.  ... 
doi:10.1145/307418.307471 fatcat:yxtrfl3nurctjg4lgpzojjgywa

Implementation of Fir Filter Using a Novel modulo Adder for 2n - 2 k -1 Residue Number System

G.V. Padmaja, B. Sarala
2014 IOSR Journal of Electronics and Communication Engineering  
In this paper, a Finite Impulse Response (FIR) filter using a novel algorithm and its Very Large Scale Integration (VLSI) implementation structure are proposed for modulo 2 n -2 k -1 adder.  ...  In the Modular adder algorithm, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries.  ...  Acknowledgement This work is carried out on the basis of the paper entitled "A Novel Modulo 2 n − 2 k − 1 Adder for Residue Number System".  ... 
doi:10.9790/2834-09433036 fatcat:e4ww2wwpf5bkvnj7satf7bqmne

Synthesis of fast-operating devices for digital signal processing based on the number­theoretic transforms

Andrey Ivashko, Igor Liberg, Denis Lunin
2020 Eastern-European Journal of Enterprise Technologies  
Consider, in particular, an adder for the Golomb numbers modulo, for which a=2, p=3⋅2 n +1.  ...  Fig. 1 . 1 Block diagram of the modulo 127 adder Fig. 3 .Fig. 4 . 34 Block diagram of the modulo p=3⋅2 n +1 adder Model of the modulo 8,191 adder Fig. 5.  ... 
doi:10.15587/1729-4061.2020.194342 fatcat:rel7yccfl5gffmh7h332frcmj4

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

Ghassem Jaberipur, Behrooz Parhami
2009 2009 19th IEEE Symposium on Computer Arithmetic  
A steady stream of published designs for modulo-(2 n ± 1) adders has gradually reduced the latency of such adders to a point where they are now quite competitive with ordinary (mod-2 n ) adders.  ...  More specifically, we devise a new redundant representation of mod-(2 n ± 1) residues that allows ordinary fast adders and a small amount of peripheral logic to be employed for modulo-(2 n ± 1) addition  ...  ACKNOWLEDGMENTS We thank Saeed Nejati for his assistance in obtaining the synthesis results reported in this paper, and Hanieh Alavi for her catching of the design flaw in [1] . G.  ... 
doi:10.1109/arith.2009.14 dblp:conf/arith/JaberipurP09 fatcat:wpiqlij6gjgipfvn2ljvpmh6w4

A systolic architecture for modulo multiplication

K.M. Elleithy, M.A. Bayoumi
1995 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
A VLSI implementation using 3 micron CMOS technology shows that a pipelined n-bit modulo multiplication scheme can operate with a throughput of 30 M operation per second. 1057-7130/95$04.00 0 1995 IEEE  ...  P. Kennedy and L. 0. Chua, "Neural networks for nonlinear programming," IEEE Trans.  ...  I P The carry bit generated from the second unit indicates whether or not 21 * zz is greater than m. A multiplexer, controlled by the carry, selects the correct output.  ... 
doi:10.1109/82.475251 fatcat:mo5orbnuf5auldprtfz6ycpl54

Modulo-(2^n -- 2^q -- 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues

Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur
2015 2015 IEEE 22nd Symposium on Computer Arithmetic  
This leads to additional performance efficiency similar to the effect of double zero representation in modulo-ሺ ‫ܖ‬ െ ሻ adders.  ...  The residue number system ૌ ൌ ሼ ‫ܖ‬ െ ǡ ‫ܖ‬ ǡ ‫ܖ‬ ሽ has been extensively studied towards perfection in realization of efficient parallel prefix modular adders, with ሺ ‫ܖܗܔ‪‬‬ ઢ۵ latency.  ...  Modulo-(ʹ െ ͳ) RPP adder ⊕ x y xy ∨ x y x y ( ) , A A G P ( ) , r r G P ( ) , ∨ A A A r r G PG P PA A r G PG ( ) , A A G P ( ) , r r G P ( ) , G P ( ) , G P B.  ... 
doi:10.1109/arith.2015.9 dblp:conf/arith/LangroudiJ15 fatcat:wvrnkb4om5glpl5c7dtvvcsgcy

Optimized Implementation of RNS FIR Filters Based on FPGAs

Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2010 Journal of Signal Processing Systems  
The implementation of modulo m adders, modulo m constant and general multipliers, input and output converters are presented.  ...  If the carry is one then S1 > m and S2 is selected as output, otherwise S1 is selected. 2.  ...  The most significant bits of the summation are therefore multiplied for the constant value 2 33 modulo M using a 2 3 × 33 ROM and the last modulo M addition is performed by using a parallel modulo adder  ... 
doi:10.1007/s11265-010-0537-y fatcat:kxl4lpljynbkhhxovga7ixvttu

New Self-Checking Booth Multipliers

Marc Hunger, Daniel Marienfeld
2008 International Journal of Applied Mathematics and Computer Science  
Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension.  ...  New Self-Checking Booth Multipliers This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction.  ...  Michael Goessel from the Fault Tolerant Computing Group at the University of Potsdam for stimulating discussions.  ... 
doi:10.2478/v10006-008-0029-4 fatcat:p2dvubgiwncotdhofe2nng4sfe

Design and Implementation of Efficient Cryptographic Arithmetic based on Reversible logic and Vedic Mathematics

Kiran Kumar V G
2020 International Journal of Advanced Trends in Computer Science and Engineering  
Montgomery modular operation is modified and its efficiency is checked with the different multipliers and the modular reduction algorithms implemented here.  ...  The portability of a device, power consumed, response time of the system, power dissipation are some of the important aspects that need to be considered while designing a system with complex operations  ...  the support for carrying out the research work.  ... 
doi:10.30534/ijatcse/2020/21922020 fatcat:nthzavqr2rhqvi672m42s323wi

Synthesis and analysis of Fourier and format number transform operator on FPGA
IJARCCE - Computer and Communication Engineering

Dr.Godbole B. B, Miss.PanditMadhuri D
2015 IJARCCE  
The systems are designed with a new architecture for this operator that makes it a device intended to perform two different transforms.  ...  In this SR context, the Fast Fourier Transform (FFT) operator is defined as a common operator for many classical telecommunications operations.  ...  Then, one need to define a modulo(F t ) multiplier, adder and subtracter. A.  ... 
doi:10.17148/ijarcce.2015.4118 fatcat:5dlyukpywjbcznozqjzr25vdji


Maksat Kalimoldayev, Sakhybay Tynymbayev, Sergiy Gnatyuk, Margulan Ibraimov, Miras Magzom
2019 NEWS of National Academy of Sciences of the Republic of Kazakhstan  
AP05132469 "Development of software-hardware facilities for cryptosystems based on the nonpositional number system").  ...  The procedure for calculating residues is given in table 1. Check example shown infigure 3.  ...  The block 3 consists of adders modulo 2 ( 2 2 ). The block 4 consists of partial remainder formers -4 ( ). At input 6, a polynomial is accepted -the module P (x).  ... 
doi:10.32014/2019.2518-170x.55 fatcat:7mo6enbqufh4zdp5ocxnonbf6a


M. Kalimoldayev, Director general of Institute of Information and computational technologies, Doctor of sciences, professor, academician member of the National academy of science of the Republic of Kazakhstan, Almaty, Kazakhstan, S. Tynymbayev, S. Gnatyuk, S. Khokhlov, M. Magzom, Y. Kozhagulov,,, Chief researcher, Candidate of Technical Sciences, Institute of Information and computational technologies, Almaty, Kazakhstan;;, Doctor of sciences, Associate Professor, Leading Researcher in Cybersecurity R&D Lab, Executive Secretary of Ukrainian Scientific Journal of Information Security, Scientific Adviser of Engineering Academy of Ukraine, IEEE Member, National aviation university, Kyiv, Ukraine;;, Lead researcher, PhD, Lecturer of Department of Physics and Technology, al-Farabi Kazakh national university, Almaty, Kazakhstan;; https:/ (+2 others)
2019 NEWS of National Academy of Sciences of the Republic of Kazakhstan  
N-1 ) , block of circuits AND 3 (AND 1 ÷ AND N-1 ), block of adders modulo two (МA 21 ÷ МA2 N-1 ), delay lines 5.  ...  To check the correctness of the proposed algorithm on the integrated circuit, a time diagram was built on the FPGA of the Artix 7 model shown in Figure 3 .  ...  To verify originality, your article may be checked by the Cross Check originality detection service  ... 
doi:10.32014/2019.2518-170x.113 fatcat:a3qgp75sojd75nujzyo2iliqna

Efficient residue comparison algorithm for general moduli sets

Shaoqiang Bi, W.J. Gross
2005 48th Midwest Symposium on Circuits and Systems, 2005.  
In this paper, we propose new residue comparison algorithms for general moduli sets and present an efficient ROM-free residue comparator for {2 n +1,2 n ,2 n −1} using the smallest modulo operation without  ...  Based on the diagonal function in [4] between Z and Z′ is the first item, MUX array, one stage of n-bit carry-save adder (CSA) with end-around-carry (EAC) and one n-bit 1's complement adder. implemented  ...  The detail structure of the A X and B X generator can be found inFigure 1. The second MUX array uses the carry-out signal C out of the subtractor x 2 −x 1 ′ as its selecting signal.  ... 
doi:10.1109/mwscas.2005.1594422 fatcat:h52t6bc47zewxgcc3i3dwndtda

Effective Reverse Converter for General Three Moduli Set{(2^n)-1,(2^n)+1,(2^(pn+1))-1}

Mehdi Hosseinzadeh, Keihaneh Kia
2012 International Journal of Image Graphics and Signal Processing  
In this system, a weighted number is converted into a set of small Residues and arithmetic operations can be performed in parallel on each modulo.  ...  Such a representation is unique for any integer X in the range [0,M-1], where M=P 1 P 2 ...P n is the dynamic range of the moduli set {P 1 ,P 2 , ...,P n }.  ...  We use the unit gate delay of parallel prefix adder for critical modulo of moduli sets of table 1, and the results are shown in table 3 .  ... 
doi:10.5815/ijigsp.2012.09.06 fatcat:bqdg3kdxkfdedf2vjfc6ckcnma
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