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Statistical Security analysis of AES with X-Tolerant Response Compactor against All Types of Test Infrastructure Attacks with/without Countermeasure

Jayesh Popat, Usha Mehta
2019 IET Circuits, Devices & Systems  
In this study, the authors investigated scan-chain attack based on different distributions of key-related flipflops of AES hardware implementation with X-tolerant response compactor-based test infrastructure  ...  In this study, the statistical security analyses are performed with and without the proposed countermeasure in case of AES hardware followed by X-tolerant test response compactor.  ...  The round register data is then compacted by using X-tolerant test compactor. The compacted response is further processed by the proposed scheme called modular exponentiation.  ... 
doi:10.1049/iet-cds.2019.0083 fatcat:fdbzqfxh4bcu3ebou5mqoxvgfq

Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

Prakash Srinivasan, Ronan Farrell
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
In this paper, we analyze the limitations of the modular test architecture.  ...  However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block.  ...  ACKNOWLEDGMENT The authors are indebted to Eamonn Ward, Donald Mcerlearn, and Desmond Fitzgerald of Intel Ireland Limited, for their guidance.  ... 
doi:10.1109/isvlsi.2010.59 dblp:conf/isvlsi/SrinivasanF10 fatcat:nhpnh5zydvdidgorwlrzksncni

Multi-Functional Converter with Integrated Motor Control, Battery Charging and Active Module Balancing for Electric Vehicular Application

Laszlo Mathe, Erik Schaltz, Remus Teodorescu, Marcos Rejas Haddioui
2014 2014 IEEE Vehicle Power and Propulsion Conference (VPPC)  
The control of the energy flow has been done through a Modular Multilevel Converter (MMC), which has demonstrated advantages over 2 level converters in terms of efficiency, fault tolerant operation, flexible  ...  In order to reduce the fuel consumption and the acoustical noise generated by refuse lorries, electrification of the waste compactor unit is a very promising solution.  ...  MODULAR MULTILEVEL CONVERTER INTRODUCTION The main idea behind modular multilevel converters (MMC) is to increase the number of discrete voltage levels at the output of the converter.  ... 
doi:10.1109/vppc.2014.7007106 fatcat:t3374lpupnf7fdjegsz5vcm2lu

A New Scan Attack on RSA in Presence of Industrial Countermeasures [chapter]

Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2012 Lecture Notes in Computer Science  
The attack is performed on an actual hardware implementation, for which different test scenarios were conceived (response compaction, X-Masking).  ...  The practical aspects of scan-based attacks on the RSA cryptosystem are also presented.  ...  This comes from a basic property of this kind of response compactors: the parity of differences measured in the test output is equal to the parity of differences in the intermediate register.  ... 
doi:10.1007/978-3-642-29912-4_8 fatcat:rn4tb6d7hnhqpfkvfqafgvprna

Resource-constrained system-on-a-chip test: a survey

Q. Xu, N. Nicolici
2005 IEE Proceedings - Computers and digital Techniques  
Manufacturing test is a key step in the implementation flow of modern integrated electronic products.  ...  In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control.  ...  Based on their structures, test response compactors can be categorized into three types [112] : infinite memory compactors (also called time compactors or sequential compactors), memoryless compactors  ... 
doi:10.1049/ip-cdt:20045019 fatcat:6ofceww26veufioqaq2wjhpnem

Test exploration and validation using transaction level models

M.A. Kochte, C.G. Zoellin, M.E. Imhof, R.S. Khaligh, M. Radetzki, H.-J. Wunderlich, S. Di Carlo, P. Prinetto
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well.  ...  The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space.  ...  ACKNOWLEDGMENT This work has been supported by the German Research Foundation (DFG) under grants Wu245/3-3 and Wu245/5-1 and by a Vigoni grant of the German Academic Exchange Service (DAAD).  ... 
doi:10.1109/date.2009.5090856 dblp:conf/date/KochteZIKRWCP09 fatcat:cu7rcp5ckzchnhvbnpjymkhwre

Numerical Model for Reinforced Soil Segmental Walls under Surcharge Loading

Kianoosh Hatami, Richard J. Bathurst
2006 Journal of Geotechnical and Geoenvironmental Engineering  
Predicted response features of each test wall are compared against measured boundary loads, wall displacements, and reinforcement strain values.  ...  Physical test measurements are unique in the literature because they include a careful estimate of the reliability of measured data.  ...  Allen during the preparation of this paper and the contribution of P. Burgess and N. Vlachopoulos ͑former graduate students͒ who carried out the physical model tests described in the paper.  ... 
doi:10.1061/(asce)1090-0241(2006)132:6(673) fatcat:o2vgcsmvhrh4xdcowo3loeige4

Security Analysis of Industrial Test Compression Schemes

Amitabh Das, Baris Ege, Santosh Ghosh, Lejla Batina, Ingrid Verbauwhede
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Test compression is widely used for reducing test time and cost of a VLSI circuit. It is also claimed to provide security against scan based side-channel attacks.  ...  This paper pursues the legitimacy of this claim and presents scan attack vulnerabilities of test compression schemes used in commercial EDA tools.  ...  This is implemented by masking the parity bitstream on the output of the test response compactor instead of the data before being captured in the scan chain.  ... 
doi:10.1109/tcad.2013.2274619 fatcat:gdate6muyjg7zizi7vjydr2ajq

Impacts of Compaction Load and Procedure on Stress-Deformation Behaviors of a Soil Geosynthetic Composite (SGC) Mass—A Case Study

Meenwah Gui, Truc Phan, Thang Pham
2020 Applied Sciences  
Fill compaction in the construction of Geosynthetic Reinforced Soil (GRS) mass is typically performed by operating a vibratory or roller compactor, which in turns imposed a compaction load in direction  ...  This paper aimed to study the impact of compaction load, compaction procedure, surcharge load and CIS on the stress-deformation behavior of GRS mass via the simulation of a 2 m high Soil Geosynthetic Composite  ...  References [15, 16] numerically simulated the response of a full scale GRS modular block retaining wall undertaken at Royal Military College and compared the simulated response with the physical data  ... 
doi:10.3390/app10186339 fatcat:axbpkl7zlzcnvg2lswnligxswu

Test cost reduction for the AMD™ Athlon processor using test partitioning

Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2007 2007 IEEE International Test Conference  
The granularity of the partitioning was the key factor in achieving the results: a 33-element partition of the AMD TM Athlon CPU chip resulted in better than a ∼80% reduction in test time compared to a  ...  , reduced test application time.  ...  Figure 2 (b) shows the interface of two wrapped modules. In Figure 2 uli in the internal test mode, and captures and shifts test responses in the external test mode.  ... 
doi:10.1109/test.2007.4437562 dblp:conf/itc/SehgalFR07 fatcat:znkozzgw4nevfdriuvxsynicie


Abdelwahab Tahsin, Rami El-Sherbiny, Abdelsalam Salem
2020 Journal of Al-Azhar University Engineering Sector  
The model verification shows that the modeling technique used in Plaxis 3D is capable of capturing qualitative trends of the instrumented MSEW response, and in most cases quantitative values are in agreement  ...  Hardening Soil (HS) constitutive model would better simulate the stressstrain relationship for sand derived/ calibrated from tri-axial test.  ...  REFERENCE INSTRUMENTED FULL SCALE MSE MODEL Full-scale physical tests of 3.6 m height geo-synthetic reinforced retaining walls with modular block facing at a batter of 8 degrees from vertical, carried  ... 
doi:10.21608/auej.2020.87862 fatcat:it2kgeynarfytngrodqvs2xuzi

Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation

Ritesh Garg, Richard Putman, Nur A. Touba
2008 Proceedings of the ... IEEE VLSI Test Symposium  
The two main advantages of the proposed approach are (1) it can provide a higher amount of compaction, and (2) it is effective for larger percentages of X's in the output response.  ...  Experimental results indicate that significant amounts of output compression can be achieved with no loss of fault coverage.  ...  05 ], and modular compactors [Rajski 06b ].  ... 
doi:10.1109/vts.2008.42 dblp:conf/vts/GargPT08 fatcat:q6cjgm65grcopis7vk7atwbxfu

Influence of reinforcement stiffness and compaction on the performance of four geosynthetic-reinforced soil walls

R. J. Bathurst, A. Nernheim, D. L. Walters, T. M. Allen, P. Burgess, D. D. Saunders
2009 Geosynthetics International  
These values were adjusted to account for the influence of different compaction methods on end-of-construction wall response.  ...  Reinforcement loads are computed from strain readings and results of in-isolation constant-load (creep) tests.  ...  of Ontario, the Department of National Defence (Canada), and the following state departments of transportation in the USA: Alaska, Arizona, California, Colorado, Idaho, Minnesota, New York, North Dakota  ... 
doi:10.1680/gein.2009.16.1.43 fatcat:yo3r3fyazvdrdhggcqy23mavve

Hardware Security in Case of Scan Based Attack on Crypto Hardware

Jayesh Popat, Usha Mehta
2018 International Journal of VLSI Design & Communication Systems  
The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure.  ...  The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.  ...  This method requires extra hardware for Test-pattern generator, response compactor and a ROM for golden signature storage on-chip.  ... 
doi:10.5121/vlsic.2018.9201 fatcat:l3awhu4juvamnjac63uaysqfpy

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures

Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Mane-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2012 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)  
Several up-to-date Design-for-Testability (DfT) features are considered, including response compaction, X-Masking and partial scan.  ...  This paper presents a scan-based attack on hardware implementations of Elliptic Curve Cryptosystems (ECC).  ...  This comes from a basic property of this kind of response compactors: the parity of the Hamming Distance at the test output is equal to the parity of the Hamming Distance at the intermediate register.  ... 
doi:10.1109/dft.2012.6378197 dblp:conf/dft/DaRoltDNFRV12 fatcat:5a5zrv77unfxto766qc4aelx2i
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