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Modified LRU policies for improving second-level cache behavior

W.A. Wong, J.-L. Baer
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)  
Both schemes improve on the second-level cache miss rate over a pure LRU algorithm, by as much as 12% in the profiling case and 20% in the dynamic case.  ...  Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches.  ...  Acknowledgments We would like to thank Chris Wilkerson (Intel MRL) and Nick Wade (Intel MRL) for providing the traces and for their insights, observations, and suggestions.  ... 
doi:10.1109/hpca.2000.824338 dblp:conf/hpca/WongB00 fatcat:z7o3ulggfvcytdiqyrt6iigf4y

A New Cache Replacement Policy for Improving Last Level Cache Performance
라스트 레벨 캐쉬 성능 향상을 위한 캐쉬 교체 기법 연구

Cong Thuan Do, Dong Oh Son, Jong Myon Kim, Cheol Hong Kim
2014 Journal of KIISE  
15 percent when compared to conventional LRU. In addition, the performance of the processor that applied our proposed cache replacement policy improved by 4.7 percent over LRU, on average.  ...  In this paper, we propose a method to improve performance of LRU replacement policy that increases the effectiveness of last level cache (second-level cache in this study).  ...  The first level cache consists of two separate caches, instruction cache and data cache while the second level cache is unified cache. Therefore, the second level cache is the last level cache.  ... 
doi:10.5626/jok.2014.41.11.871 fatcat:mkmjge66mravzmloujiqykuzfm

Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems

Dimitris Kaseridis, Muhammad Faisal Iqbal, Lizy Kurian John
2014 IEEE transactions on computers  
In this work we describe a quasi-partitioning scheme for last-level caches that combines the memory-level parallelism, cache friendliness and interference sensitivity of competing applications, to efficiently  ...  The proposed scheme improves both system throughput and execution fairnessoutperforming previous schemes that are oblivious to applications' memory behavior.  ...  a new cache line in the LRU stack per application/core, named IP i , b) a Promotion policy; the way LRU stack is modified on a cache hit, and c) a Replacement Policy: the exit point of cache-lines in  ... 
doi:10.1109/tc.2013.18 fatcat:lyqd5vduzzcdln6k7mfzbbi3yi

Write-Aware Replacement Policies for PCM-Based Systems

R. Rodríguez-Rodríguez, F. Castro, D. Chaver, R. Gonzalez-Alberquilla, L. Piñuel, F. Tirado
2014 Computer journal  
For this purpose, we present an analysis of conventional cache replacement policies in terms of the amount of writebacks to main memory they imply and we also propose some new replacement algorithms for  ...  the last level cache (LLC) with the goal of cutting the write traffic to memory and consequently to increase PCM lifetime without degrading system performance.  ...  We use the classic memory model provided by the simulator and we modify it by including a new cache level (L3) and encoding the proposed cache replacement policies.  ... 
doi:10.1093/comjnl/bxu104 fatcat:raaxiid7ivfhbh33ll6a5pdd2q

PACMan

Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely, Joel Emer
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
For multiprogrammed workloads, on a 4core CMP, PACMan improves performance by 21.5% on average.  ...  In fact, PAC-Man improves performance consistently across multimedia, games, server, and SPEC CPU2006 workloads by an average of 21.9% over the baseline LRU policy.  ...  Acknowledgements We thank the entire Intel VSSAD group for their support and feedback during this work.  ... 
doi:10.1145/2155620.2155672 dblp:conf/micro/WuJMSE11 fatcat:6kctm47hibazlgtahvz5662rbu

PAC-PLRU: A Cache Replacement Policy to Salvage Discarded Predictions from Hardware Prefetchers

Ke Zhang, Zhensong Wang, Yong Chen, Huaiyu Zhu, Xian-He Sun
2011 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing  
Cache replacement policy plays an important role in guaranteeing the availability of cache blocks, reducing miss rates, and improving applications' overall performance.  ...  The proposed PAC-PLRU policy is promising in fostering the connection between prefetching and replacement policies, and have a lasting impact on improving the overall cache performance. * † Keywords-cache  ...  Hassan Ghasemzadeh for contributions to the cache simulator. We also thank Dr. Lixin Zhang and Dr. Mingyu  ... 
doi:10.1109/ccgrid.2011.27 dblp:conf/ccgrid/ZhangWCZS11 fatcat:33uzba6edjagzmjrbogotypeke

Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Milenkovic
2004 Proceedings of the 42nd annual Southeast regional conference on - ACM-SE 42  
In order to better understand the behavior of different policies, we introduced new measures, such as cumulative distribution of cache hits in the LRU stack.  ...  The cumulative distribution of cache hits in the LRU stack indicates a very good potential for way prediction using LRU information, since the percentage of hits to the bottom of the LRU stack is relatively  ...  For second level unified cache L2U, both PLRUm and PLRUt outperform LRU for even more cache organizations than in first level caches.  ... 
doi:10.1145/986537.986601 dblp:conf/ACMse/Al-ZoubiMM04 fatcat:yy3nxllshzao7hpvbcmlol6cua

Fine Grain Cache Partitioning Using Per-Instruction Working Blocks

Jason Jong Kyu Park, Yongjun Park, Scott Mahlke
2015 2015 International Conference on Parallel Architecture and Compilation (PACT)  
Experiments show that ILRU can improve the cache performance in all levels of cache, reducing the number of misses by an average of 7.0% for L1, 9.1% for L2, and 8.7% for L3, which results in a geometric  ...  A traditional least-recently used (LRU) cache replacement policy fails to achieve the performance of the optimal replacement policy when cache blocks with diverse reuse characteristics interfere with each  ...  ACKNOWLEDGMENT We would like to thank the anonymous reviewers as well as the fellow members of the CCCP research group for their valuable comments and feedbacks.  ... 
doi:10.1109/pact.2015.11 dblp:conf/IEEEpact/ParkPM15 fatcat:mkcdwjzbvnhodl2g7b2lx3mgci

The evicted-address filter

Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Todd C. Mowry
2012 Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12  
We compare our EAF-based mechanism to ve state-of-the-art mechanisms that address cache pollution or thrashing, and show that it provides signi cant performance improvements for a wide variety of workloads  ...  In this paper, we propose a new, simple mechanism to predict the reuse behavior of missed cache blocks in a manner that mitigates both pollution and thrashing.  ...  We acknowledge members of the SAFARI and LBA groups for their feedback and for the stimulating research environment they provide.  ... 
doi:10.1145/2370816.2370868 dblp:conf/IEEEpact/SeshadriMKM12 fatcat:byttqcggj5hotmdg5vyujcpjli

Architectural support for operating system-driven CMP cache management

Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
2006 Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06  
Unfortunately, one key resource-lower-level shared cache in chip multi-processors-is commonly managed purely in hardware by rudimentary replacement policies such as least-recentlyused (LRU).  ...  For example, the cache management policy for a scenario where applications from a single organization are running under "best effort" performance expectation is likely to be different from the policy for  ...  Acknowledgments We would like to thank anonymous reviewers for their feedback. This work is supported in part by Purdue Research Foundation XR Grant No. 690 1285-4010 and Purdue University.  ... 
doi:10.1145/1152154.1152160 dblp:conf/IEEEpact/RafiqueLT06 fatcat:y6m3fj3hg5eaplx7zgpqm3u4jq

WCET analysis of instruction cache hierarchies

Damien Hardy, Isabelle Puaut
2011 Journal of systems architecture  
In this paper, we propose a safe static instruction cache analysis method for multi-level caches.  ...  We show that the method is tight in the case of non-inclusive caches hierarchies and exclusive caches hierarchies, provided that all cache levels use the Least Recently Used (LRU) replacement policy.  ...  We also wish to thank Benjamin Lesage for his help concerning the analysis of exclusive cache hierarchies, and Jan Reineke for his comments about the mls and evict bounds used to model non-LRU cache replacement  ... 
doi:10.1016/j.sysarc.2010.08.007 fatcat:rw2vm7ohvvhfrli32xtok2itvu

Optimal bypass monitor for high performance last-level caches

Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng
2012 Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12  
In the last-level cache, large amounts of blocks have reuse distances greater than the available cache capacity.  ...  Our experimental results show that using less than 1.5KB extra memory, OBM with the NRU replacement policy outperforms LRU by 9.7% and 8.9% for single-thread and multiprogrammed workloads respectively.  ...  ACKNOWLEDGMENTS We would like to thank the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/2370816.2370862 dblp:conf/IEEEpact/LiTXLC12 fatcat:mio4na2nbbdxpfve56tquje54m

Improving cache performance using read-write partitioning

Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutluy, Daniel A. Jimenezz
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
For a single-core system, RWP provides 5% average speedup across the entire SPEC CPU2006 suite, and 14% average speedup for cache-sensitive benchmarks, over the baseline LRU replacement policy.  ...  With few exceptions, cache lines that serve loads are more critical for performance than cache lines that serve only stores.  ...  We thank the anonymous reviewers for their helpful feedback, and acknowledge the support of the Intel Science and Technology Center on Cloud Computing.  ... 
doi:10.1109/hpca.2014.6835954 dblp:conf/hpca/KhanAWMJ14 fatcat:rbonj4nuybbjvgejy5jbn5ntsi

ARI

Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
Our specific focus is to reduce writebacks as much as possible while maintaining or improving miss rate relative to conventional LRU replacement policy.  ...  Policies which foster a balanced approach, between reducing write traffic to memory and improving miss-rates can increase overall performance, improve energy efficiency and memory system lifetime for NVM  ...  ACKNOWLEDGMENTS The authors would like to thank Onur Mutlu and the anonymous reviewers for their insightful comments which helped to improve the quality of this manuscript.  ... 
doi:10.1145/2543697 fatcat:2qy5fp4rt5ex5pq2y47kiyj5py

Adaptive Page Migration Policy with Huge Pages in Tiered Memory Systems

Taekyung Heo, Yang Wang, Wei Cui, Jaehyuk Huh, Lintao Zhang
2020 IEEE transactions on computers  
The proposed dynamic policy selection can achieve 23.8% performance improvement compared to a prior approximate mechanism based on LRU lists in Linux systems.  ...  The evaluation shows that none of the three migration policies excel the others, as the effectiveness of each policy depends on application behaviors.  ...  ACKNOWLEDGEMENTS We thank the anonymous reviewers for their insightful feedbacks and comments.  ... 
doi:10.1109/tc.2020.3036686 fatcat:uwpm4n6ejbbpzmoe3afunwcpt4
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