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A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, Samuel Palermo
2013 IEEE Journal of Solid-State Circuits  
A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead.  ...  Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER .  ...  ACKNOWLEDGMENT The authors would like to thank MOSIS for chip fabrication.  ... 
doi:10.1109/jssc.2013.2259036 fatcat:jzqlr3v5vzcctpmp46kyd3aioi

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications

Ehsan Zhian Tabasy, Ayman Shafik, Keytaek Lee, Sebastian Hoyos, Samuel Palermo
2014 IEEE Journal of Solid-State Circuits  
for a lower complexity back-end DSP and/or decreased ADC resolution.  ...  Index Terms-ADC-based receiver, analog to digital converter (ADC), decision feedback equalizer (DFE), embedded equalization, feed-forward equalizer (FFE), successive approximation register (SAR), time  ...  ACKNOWLEDGMENT The authors would like to thank Texas Instruments for chip fabrication. The authors also thank R. Payne from Texas Instruments for helpful discussions.  ... 
doi:10.1109/jssc.2014.2358568 fatcat:et4plyj7rzgl5kfvk6skwrzn74

A 3.1 to 10.6 GHz 100 Mb/s Pulse-Based Ultra-Wideband Radio Receiver Chipset

Fred Lee, Raul Blazquez, Brian Ginsburg, Johnna Powell, Michael Scharfstein, David Wentzloff, Anantha Chandrakasan
2006 2006 IEEE International Conference on Ultra-Wideband  
A bit-error-rate (BER) of 10 -3 was recorded at -80 dBm at a rate of 100 Mb/s for properly acquired packets in the lowest frequency band.  ...  Bit-scaling of the ADC from 1 to 5 bits reveals a 4 dB improvement in the link budget.  ...  The authors wish to acknowledge National Semiconductor for chip fabrication, and Miranda Ha for assistance in PCB assembly and discrete circuit design contributions.  ... 
doi:10.1109/icu.2006.281537 fatcat:bvt6q5b4zrf2jk5enklpxuri5e

ADC-Based Backplane Receivers: Motivations, Issues and Future

Hayun Chung
2016 JSTS Journal of Semiconductor Technology and Science  
This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity  ...  equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations.  ...  Flash ADCs with shallow time interleaving and SAR ADCs with deep time interleaving are two most popular choices for the front-end ADCs.  ... 
doi:10.5573/jsts.2016.16.3.300 fatcat:wpynhq36vrcg7l7pqvh7uftenq

Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver

Brian P. Ginsburg, Anantha P. Chandrakasan
2007 IEEE Journal of Solid-State Circuits  
A dual 500-MS/s, 5-bit ADC chip is implemented in a 0.18-m CMOS process, with both ADCs synchronized for use in an I/Q UWB receiver.  ...  Each ADC uses a 6-way time-interleaved SAR topology with full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500-MS/s operation with 7.8 mW power consumption  ...  ACKNOWLEDGMENT The authors would like to thank National Semiconductor for fabricating the chip, and N. Verma for many insightful discussions during the design process.  ... 
doi:10.1109/jssc.2006.889372 fatcat:ckwxakg2dbamxpkmlxaedcqs6i

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

Jon Guerber, Hariprasath Venkatram, Manideep Gande, Allen Waters, Un-Ku Moon
2012 IEEE Journal of Solid-State Circuits  
Index Terms-Residue shaping, successive approximation analog-to-digital converter (SAR ADC), SAR ADC redundancy, SAR switching, ternary SAR (TSAR), time quantization.  ...  by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word.  ...  Shackmann for validation and editing assistance as well as the anonymous reviewers who imparted valuable feedback for the paper.  ... 
doi:10.1109/jssc.2012.2211696 fatcat:bua4hq62mrcovpoocsqln3dvwe

2019 Index IEEE Journal of Solid-State Circuits Vol. 54

2019 IEEE Journal of Solid-State Circuits  
Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.  ...  Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.  ... 
doi:10.1109/jssc.2019.2956675 fatcat:laiuae7dtragjijttgfatsldmu

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011 IEEE Journal of Solid-State Circuits  
This paper proposes an adaptation engine for a 2 blind sampling ADC-based receiver.  ...  ACKNOWLEDGMENT The authors would like to thank Ravi Shivnaraine for his help with the measurements.  ...  It is possible to reduce the overall power consumption by using fractional sampling architectures [13] or by reducing the ADC power consumption using different ADC architectures such as SAR. 2169183  ... 
doi:10.1109/jssc.2011.2169183 fatcat:ibsnc6klijcibpwdkvuh6cg63q

A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS

Arthur Lombardi Campos, João Navarro, Maximiliam Luppe, Eduardo Rodrigues de Lima
2021 Analog Integrated Circuits and Signal Processing  
This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology.  ...  The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces  ...  Acknowledgements The authors would like to thank the Eldorado Research Institute, Campinas -SP, Brazil, for supporting the chip implementation. Funding None. Compliance with ethical standards  ... 
doi:10.1007/s10470-020-01742-6 fatcat:dh7sp3jlfjhrrfeu2veskcu5l4

A digitally compensated 1.5 GHz CMOS/FBAR frequency reference

S. Rai, Ying Su, Wei Pang, R. Ruby, B. Otis
2010 IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control  
The ultra-small form factor (0.79 mm × 1.72 mm) and low power dissipation (515 μA with 2 V supply) of a compensated FBAR oscillator present a promising alternative for the replacement of quartz crystal  ...  The 128word, 1024-bit sraM lUT is addressed by the 7-bit sar adc output.  ...  is used to amplify the analog readout voltage before sampling and digitizing with the adc. a sar adc architecture is chosen for its ultra-low power operation capability.  ... 
doi:10.1109/tuffc.2010.1447 pmid:20211770 fatcat:huvynnm3tjfpbot5cmfezb7udq

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers [article]

Fredy Solis, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2020 arXiv   pre-print
This paper introduces a backpropagation-based technique for the calibration of the mismatch errors of time-interleaved analog to digital converters (TI-ADCs).  ...  The error at the slicer of the receiver is processed using a modified version of the well known backpropagation algorithm from machine learning.  ...  Ariel Pola for his helpful advice on various technical issues related to the hardware implementation.  ... 
arXiv:2008.02914v1 fatcat:rcpt3qd5hzb3xeadgvvdrowcha

2020 Index IEEE Journal of Solid-State Circuits Vol. 55

2020 IEEE Journal of Solid-State Circuits  
., A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging; JSSC July 2020 1960-1970, see Qi, L., 2889-2901 Jang, S., see Kim, D., JSSC Jan. 2020 167-177 Jansson, J., see Jahromi  ...  ., +, JSSC Feb. 2020 261-271 A Second-Order Purely VCO-Based CT RD ADC Using a Modified DPLL Structure in 40-nm CMOS.  ...  ., +, JSSC March 2020 580-591 A Second-Order Purely VCO-Based CT RD ADC Using a Modified DPLL Structure in 40-nm CMOS. 56.9-GOPS Accelerator for Solving Partial Differential Equations.  ... 
doi:10.1109/jssc.2021.3054535 fatcat:rfm7shuowvakfgzumgtqzlod5i

The Philosophy of PCM

B.M. Oliver, J.R. Pierce, C.E. Shannon
1948 Proceedings of the IRE  
INTRODUCTION You don't have to deal with ADCs or DACs for long before running across this often quoted formula for the theoretical signal-tonoise ratio (SNR) of a converter.  ...  Remember that this formula represents the theoretical performance of a perfect N-bit ADC. You can compare the actual ADC SNR with the theoretical SNR and get an idea of how the ADC stacks up.  ...  Also for communications applications, the AD9446 16-bit, 100 MSPS ADC is optimized for high SNR (84 dB), dissipates 2.8 W, and is also designed on a BiCMOS process.  ... 
doi:10.1109/jrproc.1948.231941 fatcat:n5mzm7dp45cojmrmzpanr5zv2y

A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment

Joel Ortiz Sosa, Olivier Sentieys, Christian Roland
2018 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)  
Moreover, our TDS allows for wireless communication links to be established in conditions where this would be impossible for standard transceiver architectures.  ...  Experimental results show that the proposed Time-Diversity Scheme significantly improves Bit Error Rate (BER) compared to other techniques.  ...  The parallel architecture of time-interleaved SAR ADC, mentioned in Section V-B, allows to decrease the frequency for digital filters and therefore to improve power consumption.  ... 
doi:10.1109/nocs.2018.8512165 dblp:conf/nocs/SosaSR18 fatcat:v6gdgbll3fgqdmcfr4uwfrn2ha

A Millimeter-Wave Digital Link for Wireless MRI

Kamal Aggarwal, Kiran R. Joshi, Yashar Rajavi, Mazhareddin Taghivand, John M. Pauly, Ada S. Y. Poon, Greig Scott
2017 IEEE Transactions on Medical Imaging  
With the on-chip dipole antennas, the designed 60 GHz radio achieves a raw bit error rate (BER) of 10 −6 for a distance of 10 cm, well in excess of the raw BER specification of 10 −2 for a typical 802.11n  ...  High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI.  ...  Fraser Robb from GE Healthcare for  ... 
doi:10.1109/tmi.2016.2622251 pmid:27810803 pmcid:PMC5709036 fatcat:ukv7d6tecjez7pjk54rral5aiy
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