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Models of memory scheduling

A. K. Agrawala, R. M. Bryant
1975 Proceedings of the fifth symposium on Operating systems principles - SOSP '75  
Few of these models consider the effect of finite memory size of a machine and its impact on the memory scheduling problem.  ...  In an effort to formulate an analytical model for memory scheduling we propose four simple models and ex~nine their characteristics using simulation.  ...  Most of these models concentrate on the time varying memory requirements of a program rather than the question of overall memory scheduling.  ... 
doi:10.1145/800213.806540 dblp:conf/sosp/AgrawalaB75 fatcat:3miuckrtujhbdpecdtqcoudhvq

Scheduling memory constrained jobs on distributed memory parallel computers

Cathy McCann, John Zahorjan
1995 Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems - SIGMETRICS '95/PERFORMANCE '95  
We consider the problem of multiprocessor scheduling of jobs whose memory requirements place lower bounds on the fraction of the machine required in order to execute.  ...  How can a parallel machine be multiprogrammed with minimal overhead when jobs have minimum memory requirements? 2.  ...  Acknowledgements The authors thank Raj Vaswani and the anonymous referees for their careful readings of and comments on an earlier version of this paper.  ... 
doi:10.1145/223587.223610 dblp:conf/sigmetrics/McCannZ95 fatcat:m5s6ip6jkfgm5gdo7ygtwgtoqq

Formation of model-free motor memories during motor adaptation depends on perturbation schedule

Jean-Jacques Orban de Xivry, Philippe Lefèvre
2015 Journal of Neurophysiology  
Formation of model-free motor memories during motor adaptation depends on perturbation schedule.  ...  Here we modified the schedule of the first exposure to the perturbation in order to test whether perturbation schedule modulates the formation of model-free motor memory, which would manifest through the  ...  of the model-free motor memory that induces savings.  ... 
doi:10.1152/jn.00673.2014 pmid:25673736 pmcid:PMC4416610 fatcat:kqcexfcvqbc3fcf6bx2t2mlvzm

Scheduling of synchronous data flow models on scratchpad memory based embedded processors

Weijia Che, Karam S. Chatha
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject  ...  to the memory constraints.  ...  MOTIVATION 1) SDF Scheduling : The left hand of Figure 2 shows a simple SDF model.  ... 
doi:10.1109/iccad.2010.5654150 dblp:conf/iccad/CheC10 fatcat:efexbvoz4zc2hp74uyxqpgr56y

Model-based reinforcement learning under concurrent schedules of reinforcement in rodents

N. Huh, S. Jo, H. Kim, J. H. Sul, M. W. Jung
2009 Learning & memory (Cold Spring Harbor, N.Y.)  
In simple reinforcement learning algorithms, value functions are updated only by trial-and-error, whereas they are updated according to the decision-maker's knowledge or model of the environment in model-based  ...  The results show that goal choice probability increased as a function of the number of consecutive alternative choices in the latter, but not the former task, indicating that the animals were aware of  ...  Acknowledgments We thank Daeyeol Lee for helpful comments on the initial version of the manuscript. This work was supported by the Korea Research  ... 
doi:10.1101/lm.1295509 pmid:19403794 fatcat:pxa6xfdatfennfwyl5fs74yg4q

Design and Implementation of Gains Scheduled PI Control System for Shape Memory Alloy Actuator

Mohamed Alsayed Ahmed, Abdel Halim Bassiuny, Elsayed Mokhtar Bakr
2013 International Journal of Modeling and Optimization  
In this paper, the concept of model-based control of SMA actuators is introduced. Time variable parameter (TVP) model is used to describe the actuator dynamics.  ...  Experimental evaluation of gains schedule PI controller for SMA actuators shows stable and robust response that could compensate for the nonlinear phenomenon of these actuators.  ...  In this paper an effective gains schedule PI controller for shape memory alloy actuator was developed.  ... 
doi:10.7763/ijmo.2013.v3.249 fatcat:4pqwhzmhwzenrguwexglol43wa

Providing fairness on shared-memory multiprocessors via process scheduling

Di Xu, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Zhenjiang Wang
2012 Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems - SIGMETRICS '12  
For memory-intensive workloads, FPS also improves system fairness by an average of 45.2% and 21.1% on 4-core and 8-core system respectively at the expense of a throughput loss of about 2%. 1  ...  It exacerbates the need for Quality of Service (QoS) on such systems. In this paper, we propose a fair-progress process scheduling (FPS) policy to improve system fairness.  ...  Because of the complicated working mechanism in memory devices and their interactions with the processor pipeline, precise analytical modeling of performance is still very difficult.  ... 
doi:10.1145/2254756.2254792 dblp:conf/sigmetrics/XuWYLW12 fatcat:fje4d267yfgwbhjbkbcqt4x3wy

Scheduling directives for shared-memory many-core processor systems

Oded Green, Yitzhak Birk
2013 Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM '13  
We consider many-core processors with task-oriented programming, whereby scheduling constraints among tasks are decided offline, and are then enforced by the runtime system.  ...  We extend the conventional Start-After-Complete (precedence) constraint to also be usable between replicas of different such tasks rather than only between entire tasks, thereby increasing the exposable  ...  In our work, we used Plurality's shared-memory many-core system as a reference system for the incorporation of new scheduling directives.  ... 
doi:10.1145/2442992.2443005 dblp:conf/ppopp/GreenB13 fatcat:4jt5ahtxmfccvjzylzdy6apxhe

An ACT-R Model of Memory Applied to Finding the Optimal Schedule of Practice

Philip I. Pavlik, John R. Anderson
2018
Perhaps the most important of these questions is how the practices for each item should be scheduled.  ...  When a person confronts the task of memorizing a collection of facts some questions have to be answered about how to optimize their learning.  ...  Acknowledgments Preparation of this paper was supported by grant N00014-96-01-1491 from the Office of Naval Research.  ... 
doi:10.1184/r1/6613415 fatcat:hkunqlz4gvfpfn7tyi32lig6gm

GENERALIZED NET MODEL OF SCHEDULE FOR ELIMINATION OF CONFLICTS AT THE PACKET CROSSBAR SWITCH WITH MINIMUM MEMORY USING

Tashev, Kolchakov, Tasheva
2004 Fifth Int. Workshop on GNs   unpublished
It must posses modeling power with possibilities for simultaneous presentation as of data flow as of controlling actions.  ...  It may also modell a parallelism of interactions, to leave time scale, and no at last to have graphical form.  ... 
fatcat:7pqgk3arzjdedlfyvpcq7m2quu

Effects of Memory Performance on Parallel Job Scheduling [chapter]

G. Edward Suh, Larry Rudolph, Srinivas Devadas
2001 Lecture Notes in Computer Science  
Given a schedule of jobs in a shared-memory multiprocessor (SMP), and an isolated miss-rate versus memory size curve for each job, we use an analytical memory model to estimate the overall memory miss-rate  ...  We develop a new metric for job scheduling that includes the effects of memory contention amongst simultaneously-executing jobs that share a given level of memory.  ...  Effectively, the model provides a new cost function of memory performance, and any scheduler can be modified to incorporate memory considerations by adding this new cost function from the model.  ... 
doi:10.1007/3-540-45540-x_8 fatcat:oeq4gx7245bjvkihocue6rmpua

Out-of-core Training for Extremely Large-Scale Neural Networks With Adaptive Window-Based Scheduling [article]

Akio Hayakawa, Takuya Narihira
2020 arXiv   pre-print
Under a given memory budget constraint, our scheduling algorithm locally adapts the timing of memory transfers according to memory usage of each function, which improves overlap between computation and  ...  We propose a novel out-of-core algorithm that enables faster training of extremely large-scale neural networks with sizes larger than allotted GPU memory.  ...  Our model is the first to schedule memory transfers for training neural networks with locally adaptive distance by modeling the memory usage, which can find a faster schedule than existing methods. • We  ... 
arXiv:2010.14109v1 fatcat:dvftcewz3bebdpjxvun22yir5y

Variable partitioning and scheduling of multiple memory architectures for DSP

Q. Zhuge, B. Xiao, E.H.-M. Sha
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
We also present a scheduling algorithm that takes advantages of multiple memory modules, Rotation Scheduling with Variable Re-partition (RSVR).  ...  It produces more feasible solutions on a set of schedule length requirement. And our solution have less functional units that Interference Graph model.  ...  the schedule lengths produced by list scheduling with partitions of Interference Graph model [3] .  ... 
doi:10.1109/ipdps.2002.1016516 dblp:conf/ipps/ZhugeXS02 fatcat:kk4pgbjacnemne3ny4qdwx2byq

Concurrency Compliant Embedded System Modeling Methodology

Sifat Islam, Ravi Shankar, Ankur Agarwal, Andrew Katan, Cyril-Daniel Iskander
2008 2008 2nd Annual IEEE Systems Conference  
We have applied this methodology to develop process management and memory management aspects of a Real Time Operating System (RTOS).  ...  The Memory is modeled as a Quantity Resource that contains a certain number of units that can be allocated to a process. Fig. 20 : 20 The Memory Manager model.  ...  Fig 15 : 15 LTSA analyzer for Memory Manager. Fig. 16 : 16 The RTOS system. Fig. 17 : 17 The Process model. Fig. 18 : 18 The Slave CPU model. Fig. 19 : 19 The Scheduler model.  ... 
doi:10.1109/systems.2008.4519019 fatcat:56zfqtpt4fdlney4mqlag7k2dy

A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

Matheus Schuh, Claire Maiza, Joel Goossens, Pascal Raymond, Benoit Dupont de Dinechin
2020 2020 IEEE Real-Time Systems Symposium (RTSS)  
We focus on the runtime environment assuming global static scheduling, time-triggered and non-preemptive execution of tasks.  ...  models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.  ...  Acknowledgment This work was performed in the scope of the ES3CAP research project, under the Bpifrance Invest for the Future Program (Programme d'Investissements d'Avenir -PIA).  ... 
doi:10.1109/rtss49844.2020.00034 fatcat:72fpqlkk5zgsbiqfkjixbem3f4
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