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Speed binning aware design methodology to improve profit under parameter variations
2006
Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06
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In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. ...
Finally, we present an integrated design methodology for simultaneous sizing and bin placement to enhance profit under an area constraint. ...
CONCLUSIONS We have proposed a profit-aware yield model and a statistical design methodology to optimize design profit for a given price profile under an area constraint. ...
doi:10.1145/1118299.1118466
fatcat:mmhj5etk4ng5rokfzbzbyf2dka
A new methodology for concurrent technology development and cell library optimization
1999
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)
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To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of predictive simulation tools ...
This paper focuses on our approach for concurrent development of new technologies and optimization of cell libraries for these technologies. ...
The use of physically based models, coupled with a robust calibration methodology, allows for high confidence in predicting SPICE parameters for a technology under development. ...
doi:10.1109/icvd.1999.745118
dblp:conf/vlsid/ChewSCMS99
fatcat:gncaatiu5bgzfhwp3hhsa2owqi
Impact of design-manufacturing interface on SoC design methodologies
2004
IEEE Design & Test of Computers
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Some of these approaches are based on simple postprocessing steps that design methodology developers can easily integrate in the layout design subflow. ...
This model can also directly optimize circuits for yield, a use that has become common practice for very sensitive analog circuits, such as oscillators, regulators, and phased-locked loops. ...
doi:10.1109/mdt.2004.13
fatcat:2boowfvhfvbb3go6kxe35m647u
Death, taxes and failing chips
2003
Proceedings of the 40th conference on Design automation - DAC '03
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Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. ...
This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. ...
It is already a complicated and tedious task to produce adequate models for a case-based timing sign-off methodology. ...
doi:10.1145/775919.775921
fatcat:i7wwbis2urehjc62byywgik3ya
Death, taxes and failing chips
2003
Proceedings of the 40th conference on Design automation - DAC '03
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Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. ...
This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. ...
It is already a complicated and tedious task to produce adequate models for a case-based timing sign-off methodology. ...
doi:10.1145/775832.775921
dblp:conf/dac/Visweswariah03
fatcat:dmneezinb5dtngemzqesgrph5e
Near-Term Industrial Perspective of Analog CAD
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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This paper will present a reality check on the current state of the art of AMS design tools for industrial usage. ...
Analog and mixed-signal CAD looks like a nice success story: there's been significant research in building design automation tools since the late 80's, and commercial tools have been on the market for ...
Lastly, for designers to adopt a new automation tool, the new tool must help them solve real design problems that are difficult to tackle with the existing design methodology. ...
doi:10.1109/iccad.2006.320156
fatcat:obm4y7tv5nci3a7mzkur2v74ku
Near-term industrial perspective of analog CAD
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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This paper will present a reality check on the current state of the art of AMS design tools for industrial usage. ...
Analog and mixed-signal CAD looks like a nice success story: there's been significant research in building design automation tools since the late 80's, and commercial tools have been on the market for ...
Lastly, for designers to adopt a new automation tool, the new tool must help them solve real design problems that are difficult to tackle with the existing design methodology. ...
doi:10.1145/1233501.1233592
dblp:conf/iccad/Labrecque06
fatcat:2pvomuitjfhinldnnv275kp56e
Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs
2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15
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Next, we conduct hypothesis testing based on the MC-JK technique combined with Latin hypercube sampling in a statistical run-time verification environment. ...
This paper proposes a Monte Carlo-Jackknife (MC-JK) technique, a variant of Monte Carlo method, to verify process variation affecting the performance and functionality of AMS designs. ...
Based on repetitive simulations, it permits to evaluate substantive design properties as well as to statistically estimate circuit parameters. ...
doi:10.1145/2742060.2742122
dblp:conf/glvlsi/SeghaierZT15
fatcat:omvqbrm4gzg5leloxpnbwpjyrq
Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian model fusion
2012
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12
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A circuit example designed in a commercial 32 nm CMOS process is used to demonstrate the efficacy of the proposed post-silicon performance modeling and tuning methodology based on BMF. ...
This talk presents a novel Bayesian Model Fusion (BMF) technique for efficient post-silicon performance modeling and tuning of analog and mixed-signal (AMS) circuits. ...
ACKNOWLEDGEMENTS The author acknowledges the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity ...
doi:10.1145/2429384.2429503
dblp:conf/iccad/Li12
fatcat:ucrgdeo5ojgnli5enftu3yum6i
Perspectives on technology and technology-driven CAD
2000
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. ...
For the deep submicrometer (DSM) devices, these tools provide a better insight than any measurement techniques and they have become indispensable in the new device creation. ...
Kibarian of PDF Solutions for valuable discussions. They would also like to thank Dr. Z. Yu and Dr. D. Yergeau of Stanford University for their help in the manuscript preparation. ...
doi:10.1109/43.898831
fatcat:unwzr43rpzf2lpj5vcnnoth24q
Automation in mixed-signal design
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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We discuss new design methodologies and EDA tools that are being or need to be developed to address the problems of designing such mixed-signal integrated systems. ...
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. ...
ACKNOWLEDGEMENTS Funding for the reported research results is acknowledged from IWT/Medea+ Uppermost, Solido Design Automation and FWO Flanders. ...
doi:10.1145/1233501.1233594
dblp:conf/iccad/McConaghyG06
fatcat:pzumqfgnbvcnvmh6aukedf2egq
Automation in Mixed-Signal Design: Challenges and Solutions in the Wake of the Nano Era
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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We discuss new design methodologies and EDA tools that are being or need to be developed to address the problems of designing such mixed-signal integrated systems. ...
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. ...
ACKNOWLEDGEMENTS Funding for the reported research results is acknowledged from IWT/Medea+ Uppermost, Solido Design Automation and FWO Flanders. ...
doi:10.1109/iccad.2006.320158
fatcat:6ncitfxrgbacjarc6rfzy3lz7u
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects
2000
Proceedings of the 37th conference on Design automation - DAC '00
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This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. ...
A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability ...
In this paper we present a new methodology that allows statistical simulation of a large number of devices subject to intra-die variability. ...
doi:10.1145/337292.337302
dblp:conf/dac/GaurdianiSMSC00
fatcat:iiacc5jjcjdjtau6efvnvep4mi
The Effect of Exchange Rate Volatility on Stock Return in Taiwan Around Abenomics
2017
Asian Economic and Financial Review
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of currency are over 2.3% and 2.72% for automotive and integrated circuits industries, respectively. ...
Therefore, the main contribution of this paper is to provide a means for CEOs of companies in the two industries to exercise hedge options and evade the risk of exchange rate for their firms when the appreciation ...
before tax ratio for the integrated circuits industry, based on the volatility of exchange rate. ...
doi:10.18488/journal.aefr/2017.7.4/102.4.368.380
fatcat:4hi4lglvnjdyxb4itsvdapdirm
Guest Editors' Introduction: DFM Drives Changes in Design Flow
2005
IEEE Design & Test of Computers
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IEEE Design & Test of Computers DESIGN FOR MANUFACTURABILITY (DFM) has thus far been the focus of extensive study in the semiconductor industry. ...
To help address this situation, new classes of DFM methods, tools, and IP have emerged. ...
between design-rule-versus tool-based DFM methodologies. ■ New manufacturability-oriented design blocks. ...
doi:10.1109/mdt.2005.61
fatcat:hgrbagcembgvjdzvwuxhc4vvvi
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