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Modeling buffers with data refresh semantics in automotive architectures

Linh Thi Xuan Phan, Reinhard Schneider, Samarjit Chakraborty, Insup Lee
2010 Proceedings of the tenth ACM international conference on Embedded software - EMSOFT '10  
In this paper we propose an analytical framework for accurately modeling such data refresh semantics. Our model exploits a novel feedback control mechanism and is purely functional in nature.  ...  In this paper we propose an analytical framework for accurately modeling such data refresh semantics. Our model exploits a novel feedback control mechanism and is purely functional in nature.  ...  Figure 2 : A system with a buffer having data refresh semantics. Basic modeling ideas.  ... 
doi:10.1145/1879021.1879038 dblp:conf/emsoft/PhanSCL10 fatcat:3szefrslrjeubbxakkyfl273oa

The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092)

Rolf Ernst, Stefan Kuntz, Sophie Quinton, Martin Simons, Michael Wagner
2018 Dagstuhl Reports  
the automotive industry with the shift to multicore architectures.  ...  The main purpose was to promote a closer interaction between the subcommunities involved in the application of LET to multicore systems, with a particular emphasis on the automotive domain.  ...  This abstract presents two active lines of work in our group dealing with these questions: (1) LET applied to legacy automotive systems including multi-core architectures, and (2) LET in the context of  ... 
doi:10.4230/dagrep.8.2.122 dblp:journals/dagstuhl-reports/ErnstKQS18 fatcat:6k7z4uyijrhuxceulih3jeiqoa

A Modeling Paradigm for Integrated Modular Avionics Design

Abdoulaye Gamati, Christian Brunette, Romain Delamare, Thierry Gautier, Jean-pierre Talpin
2006 32nd EUROMICRO Conference on Software Engineering and Advanced Applications (EUROMICRO'06)  
modular avionics architectures.  ...  Its descriptions can be therefore transformed into POLYCHRONY's models in order to access the available formal tools and techniques for validation.  ...  ); (b) Fuel indicator that updates the report message (produced by Position indicator) with the current fuel level information; and (c) Parameter refresher that refreshes all the global parameters used  ... 
doi:10.1109/euromicro.2006.11 dblp:conf/euromicro/GamatieBDGT06 fatcat:ovlhvslojzhxtg2krqqcazgksa

Fault Resilient Real-Time Design for NoC Architectures

Christopher Zimmer, Frank Mueller
2012 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems  
Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming common in COTS.  ...  These architectures benefit real-time scheduling, but they also pose predictability challenges.  ...  In addition, rejuvenation with refreshed data was realized as an optional extension. This allow us to compare the time (overhead) for convergence with and without refresh.  ... 
doi:10.1109/iccps.2012.16 dblp:conf/iccps/ZimmerM12 fatcat:2hnpfqjjn5dpzgch7moi4u7cbe

Validate, simulate, and implement ARINC653 systems using the AADL

Julien Delange, Laurent Pautet, Alain Plantec, Mickael Kerboeuf, Frank Singhoff, Fabrice Kordon
2009 Proceedings of the ACM SIGAda annual international conference on Ada and related technologies - SIGAda '09  
It details a modeling approach exploiting the new features of AADL version 2 for the design of ARINC653 architectures.  ...  The Architecture Analysis and Design Language (AADL) proposes a component-based language suitable to operate MDE that fits with safety-critical systems needs.  ...  A complete list of the contributors is available in the documentation of POK.  ... 
doi:10.1145/1647420.1647435 dblp:conf/sigada/DelangePPKSK09 fatcat:7lfuqd536fg6xjr7434vz3arqy

Modeling a system controller for timing analysis

Stephan Thesing
2006 Proceedings of the 6th ACM & IEEE International conference on Embedded software - EMSOFT '06  
This paper is the first to describe experience in deriving a timing model for such a system controller.  ...  A successful timing analysis approach developed at Saarland University/AbsInt GmbH uses abstract interpretation to derive safe WCET bounds based on timing models of the processor and periphery in a system  ...  Modern architectures with caches, pipelines, buffers, etc. are very sensitive to small changes in the execution state, because the performance of those components is very execution history sensitive, e.g  ... 
doi:10.1145/1176887.1176929 dblp:conf/emsoft/Thesing06 fatcat:77r2aboernabnagjjxgvzkua6i

Mega-Modeling of complex, distributed, heterogeneous CPS systems

Eugenio Villar, Hector Posadas, Rafik Henia, Laurent Rioux
2020 Microprocessors and microsystems  
The model is flexible enough to be adapted to different architectural solutions with a minimal effort by changing its underlying Model of Computation and Communication (MoCC).  ...  Addressing these challenges require flexible design technologies able to support from a single-source model its architectural mapping to different computing resources, of different kind and in different  ...  Components may generate data and consume data at any time. This means that in the general case, a buffer is needed to store data when, during some period, there are more date produced than consumed.  ... 
doi:10.1016/j.micpro.2020.103244 fatcat:su7d3t6l4zhl5nxzmrui5vn7oq

TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis

Daniel Kästner, Markus Pister, Simon Wegener, Christian Ferdinand, Michael Wagner
2019 Worst-Case Execution Time Analysis  
For high-performance multi-core architectures with degraded timing predictability, WCET bounds can be computed by hybrid WCET analysis which combines static analysis with timing measurements.  ...  If the application is safety-relevant, worst-case execution time bounds have to be determined in order to demonstrate deadline adherence.  ...  A prerequisite is that good models of the processor/System-on-Chip (SoC) architecture can be determined.  ... 
doi:10.4230/oasics.wcet.2019.1 dblp:conf/wcet/Kastner0WF19 fatcat:uoscp7v7nfecbaxit6vq54w2aq

Design for Timing Predictability

Lothar Thiele, Reinhard Wilhelm
2004 Real-time systems  
The ultimate goal is to design performant systems with sharp upper and lower bounds on execution times.  ...  Trends in hardware and software design run contrary to predictability.  ...  In particular, many results are available concerning the predictability of restricted data¯ow models such as synchronous data¯ow (SDF) graphs.  ... 
doi:10.1023/b:time.0000045316.66276.6e fatcat:m6bkbjiqezap7kd3jhtbmamdem

Determining Bounds on Execution Times [chapter]

Reinhard Wilhelm
2009 Industrial Information Technology  
In modern microprocessor architectures, caches, pipelines, and all kinds of speculation are key features for improving (average-case) performance.  ...  These systems are typically subject to stringent timing constraints, which often result from the interaction with the surrounding physical environment.  ...  Simple Architectures without Timing Anomalies In a first step, we assume a simple processor architecture, with in-order execution and without timing anomalies, i.e., architectures, where local worst cases  ... 
doi:10.1201/9781439807637.ch9 fatcat:v2xveguwx5co5p2ydhxwabpucy

Real-time Connectors for Deterministic Data-flow

Irfan Hamid, Elie Najm
2007 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007)  
In this paper we introduce deterministic bridge connectors, a type of construct that ensures deterministic data-flow communication in asynchronous real-time systems.  ...  We also present a methodology for generating these connectors automatically from the application's architecture description in order to reduce programmer effort and the chance of error.  ...  With these connectors, code generated from AADL models to run on Ravenscar-compliant kernels is faithful to the semantics of data ports as given in the standard.  ... 
doi:10.1109/rtcsa.2007.58 dblp:conf/rtcsa/HamidN07 fatcat:qd7amx4kq5hjlcsb6ltaki5zzq

Building timing predictable embedded systems

Philip Axer, Christine Rochange, Maurice Sebastian, Reinhard Von Hanxleden, Reinhard Wilhelm, Wang Yi, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson (+2 others)
2014 ACM Transactions on Embedded Computing Systems  
that provides timing semantics for a mainstream programming language (in this case C).  ...  Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment  ...  Refreshes are accounted for conservatively assuming that any transaction might interfere with an ongoing refresh.  ... 
doi:10.1145/2560033 fatcat:vyvehgnkxfdmnbs2wcwada3sxi

Polychronous design of embedded real-time applications

Abdoulaye Gamatié, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin
2007 ACM Transactions on Software Engineering and Methodology  
The expressiveness of its underlying semantics allows dealing with several issues of real-time design.  ...  The multiclock or polychronous model stands out from other synchronous specification models by its capability to enable the design of systems where each component holds its own activation clock as well  ...  For instance, P 1 only needs to read refreshed data of the same type. In this case, only the latest occurrences of messages are relevant.  ... 
doi:10.1145/1217295.1217298 fatcat:jtos7pkvtnfnlbr6vgp2z6cr5m

Modular avionics for seamless reconfigurable UAS missions

Juan Lopez, Pablo Royo, Cristina Barrado, Enric Pastor
2008 2008 IEEE/AIAA 27th Digital Avionics Systems Conference  
This need of both flexibility and complexity management while keeping low costs in the UAS avionics field requires new architectures to cope with.  ...  In this article, we describe a modular avionics architecture based on services.  ...  I.e. we may create a service that subscribes to mailbox data, stores it using the Buffer or the Blackboard semantics and provides it on demand to any consumer service using Remote Invocation.  ... 
doi:10.1109/dasc.2008.4702748 fatcat:6pat3wwamndfxoi5indxm4n4je

T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber (+11 others)
2015 Journal of systems architecture  
With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.  ...  Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.  ...  Note that refresh is not included in the WCET of memory transactions, but modeled as a high-priority periodic task during schedulability analysis of the system.  ... 
doi:10.1016/j.sysarc.2015.04.002 fatcat:yts4coszkbg7vbes3b4hzdyzui
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