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Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors

M. Saint-Laurent, M. Swaminathan
2004 IEEE Transactions on Advanced Packaging  
This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors.  ...  First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths.  ...  A chip-scale noise event can produce a relatively uniform supply voltage for the devices of a particular interconnect-dominated path located in one region of the chip and a different (but still relatively  ... 
doi:10.1109/tadvp.2004.825480 fatcat:2jbyoqvbrje47egmbzjg22nrhi

A clock distribution network for microprocessors

P.J. Restle, T.G. McNamara, D.A. Webber, P.J. Camporese, K.F. Eng, K.A. Jenkins, D.H. Allen, M.J. Rohn, M.P. Quaranta, D.W. Boerstler, C.J. Alpert, C.A. Carter (+4 others)
2001 IEEE Journal of Solid-State Circuits  
He holds four patents, has written 15 papers, and has given several invited talks and tutorials on high-frequency on-chip interconnects. Dr.  ...  Restle received IBM awards for the S/390 G4 and G5 microprocessors in 1997 and 1998, and for the invention of a high-performance VLSI clock distribution design methodology in 2000. Timothy G.  ...  Bucelot, and M. Rosenfield of the IBM Research Division, as well as D. Hoffman and C. Anderson of the IBM Enterprise Systems Group, for many valuable interactions.  ... 
doi:10.1109/4.918917 fatcat:c2564ix42rcfxo5bez7xqupoqe

Heterogeneous architecture models for interconnect-motivated system design

Sek Meng Chai, T.M. Taha, D.S. Wills, J.D. Meindl
2000 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process.  ...  Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for  ...  Davis for his homogeneous wirelength models, and P. Zarkesh-Ha for his research in heterogeneous wiring models.  ... 
doi:10.1109/92.902260 fatcat:pvag4oeoxnbhdd4jfadmschthy

Basic issues in microprocessor architecture

M.J. Flynn
1999 Journal of systems architecture  
Architectures and implementations that span these limits are vital to the continued evolution of the microprocessor.  ...  The evolution of microprocessor architecture depends upon the changing aspects of technology.  ...  Journal of Systems Architecture'99  ... 
doi:10.1016/s1383-7621(98)00045-9 fatcat:r5ewvlztafhwrnlmowblcw6vem

The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603 and PowerPC 604 RISC microprocessors

J. Parry, H. Rosten, G.B. Kromann
1998 IEEE transactions on components, packaging, and manufacturing technology. Part A (Print)  
Thermal resistance networks or "compact" models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection / ceramic-ball-grid-array (C4/CBGA) single-chip package are derived  ...  from "detailed" three-dimensional conduction models of the parts by both analytical and data fitting techniques.  ...  Lasance (Philips Research, Netherlands) and H. Vinke (Philips CFT, Netherlands) for their essential contributions to this part of the DELPHI project.  ... 
doi:10.1109/95.679039 fatcat:2kkdohevcjhofppxtzcnjkv7oa

Impact of small process geometries on microarchitectures in systems on a chip

D. Sylvester, K. Keutzer
2001 Proceedings of the IEEE  
We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs.  ...  In light of this new system-on-a-chip microarchitecture, we then examine global interconnect issues.  ...  Shilman for information on packet-switched networks.  ... 
doi:10.1109/5.920579 fatcat:xvpfrpy5rzgcnbancnnqenl27y

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Mile Stojcev, Teufik Tokic, Ivan Milentijevic
2004 Facta universitatis - series Electronics and Energetics  
This paper overviews some of the microarchitectural techniques that are typical for contemporary high-performance microprocessors.  ...  In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance.  ...  On-chip physical interconnections will present a limiting factor for performance, and possibly for energy consumption.  ... 
doi:10.2298/fuee0403285s fatcat:gaxelp2aebbnvinhxssaydxhvy

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

Ichiang Lin, Chien-In Henry Chen
2002 VLSI design (Print)  
Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to  ...  Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately.  ...  TABLE I I Semiconductors for high-performance IC in the year 2005 Process technology 0.1 micron Total No. of transistors 200 M Total No. of logic gates 40 M Chip size 520 mm £ mm On-chip clock  ... 
doi:10.1080/1065514021000012183 fatcat:wukbgvs5njcqxcsjyj7fq4tfum

A global wiring paradigm for deep submicron design

D. Sylvester, K. Keutzer
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits.  ...  for Semiconductors (NTRS) performance expectations from being met.  ...  This companion paper to [1] seeks to analyze and quantify the global impact of interconnect on future high-performance designs as outlined in the 1997 National Technology Roadmap for Semiconductors (  ... 
doi:10.1109/43.828553 fatcat:oqf42mm6kbcqngdkuhohquixeq

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS

Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael Huang, Hui Wu (+1 others)
2016 Microelectronics Journal  
The design of transmitter circuits for the 3-D integrated free-space optical interconnect system is discussed, and simulated extrapolated results on operating frequency and bandwidth are provided.  ...  The microprocessor operates at 333 MHz and includes a bus width of 64 bits, requiring a FSOI bandwidth of 10.65 Gbps after serialization.  ...  The performance of the proposed interconnect is analyzed. A number of conventional interconnect configurations are modeled for comparison.  ... 
doi:10.1016/j.mejo.2015.10.004 fatcat:tijftcud3rafzkuicaqbuadaru

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution

G. G. Lopez, G. Fiorenza, T. Bucelot, P. Restle, M. Y. Lanzerotti
2005 Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05  
A characterization of the capacitive load is needed because the contributions of the on-chip devices and interconnections are typically overestimated and are not well understood for high performance microprocessors  ...  Analysis of the data shows that the wire contribution to the chip capacitive load is significant and can increase the capacitive load of a design by 30% on average and by as much as 130% for some designs  ...  DISCUSSION The previous section provides the first characterization of the interconnection contributions to the capacitive load on a global clock distribution in a high-performance microprocessor.  ... 
doi:10.1145/1057661.1057672 dblp:conf/glvlsi/LopezFBRL05 fatcat:iohpgmpnircpbebgdj46osiloy

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

Lin Zhang, A. Carpenter, B. Ciftcioglu, A. Garg, M. Huang, Hui Wu
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors.  ...  A test chip distributing 5-GHz clock is implemented in a standard 0.18-m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.  ...  We expect the benefits of this new clocking scheme will be even greater when it is applied to high-performance multi-core microprocessors and other high performance SoC systems. Fig. 2 . 2 ILO.  ... 
doi:10.1109/tvlsi.2008.2000976 fatcat:3a3s7y7uhvg2fayod7njp4ptka

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability.  ...  In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.  ...  ACKNOWLEDGEMENTS This work was supported in part by a seed grant from the Boeing Corporation, UC-MICRO/Intel grant, NSF Grant CNS-0524771, and NSF Career Grant CCF-0448654.  ... 
doi:10.1145/1146909.1147160 dblp:conf/dac/LoiASLSB06 fatcat:7cuyik4tyjajnnyon4evhetnna

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

G.L. Loi, B. Agrawal, N. Srivastava, Sheng-Chih Lin, T. Sherwood, K. Banerjee
2006 Proceedings - Design Automation Conference  
While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability.  ...  In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.  ...  ACKNOWLEDGEMENTS This work was supported in part by a seed grant from the Boeing Corporation, UC-MICRO/Intel grant, NSF Grant CNS-0524771, and NSF Career Grant CCF-0448654.  ... 
doi:10.1109/dac.2006.229426 fatcat:wohlysaxcrgr5fw5n6mv5v6zwa

SimpleFit: a framework for analyzing design trade-offs in Raw architectures

C.A. Moritz, Donald Yeung, A. Agarwal
2001 IEEE Transactions on Parallel and Distributed Systems  
Based on an architectural model, an application model, and a VLSI cost analysis, the framework computes the performance of applications and uses an optimization process to identify designs that will execute  ...  Our model is also generalizable to multiprocessors on a chip.  ...  The authors are grateful to Tom Knight, Jonathan Babb, and Matt Frank for many relevant discussions on cost modeling, and the anonymous reviewers for their very valuable comments and help with earlier  ... 
doi:10.1109/71.940747 fatcat:trzaxxmj7vb63ougqfclbrvshe
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