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Modeling superscalar processors via statistical simulation

S. Nussbaum, J.E. Smith
Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques  
Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program.  ...  This information is then used to generate a synthetic instruction trace that is fed to a simple processor model, along with cache and branch prediction statistics.  ...  Processor Model We developed a statistical model of a superscalar processor core, using SimpleScalar [1] as a guide.  ... 
doi:10.1109/pact.2001.953284 dblp:conf/IEEEpact/NussbaumS01 fatcat:e277cdlnb5b7da2uzcd5pxduqe

Automated design of application specific superscalar processors

Tejas S. Karkhanis, James E. Smith
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Analytical modeling is applied to the automated design of application-specific superscalar processors.  ...  The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area.  ...  Fig. 1: Superscalar Processor Template Program Statistics The following set of application program statistics drive the automated design framework.  ... 
doi:10.1145/1250662.1250712 dblp:conf/isca/KarkhanisS07 fatcat:pmvkhmofira2rjnkj46lboxfl4

Automated design of application specific superscalar processors

Tejas S. Karkhanis, James E. Smith
2007 SIGARCH Computer Architecture News  
Analytical modeling is applied to the automated design of application-specific superscalar processors.  ...  The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area.  ...  Fig. 1: Superscalar Processor Template Program Statistics The following set of application program statistics drive the automated design framework.  ... 
doi:10.1145/1273440.1250712 fatcat:7apekedwtvf5zbkyvbbdb6expa

Accurately approximating superscalar processor performance from traces

Kiyeon Lee, Shayne Evans, Sangyeun Cho
2009 2009 IEEE International Symposium on Performance Analysis of Systems and Software  
Trace-driven simulation of superscalar processors is particularly complicated.  ...  Our work forms a basis for fast, accurate, and configurable multicore processor simulation using a pre-determined processor core design.  ...  Noonburg and Shen [18] have proposed a framework for statistical modeling of superscalar processors.  ... 
doi:10.1109/ispass.2009.4919655 dblp:conf/ispass/LeeEC09 fatcat:hhq4ihnt7jd63dscz3b7xwh7ky

A study of control independence in superscalar processors

E. Rotenberg, Q. Jacobson, J. Smith
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
This is followed by a more detailed set of simulations, where the key implementation features are realistically modeled. These simulations show typical performance improvements of 10-30%.  ...  Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors.  ...  This model represents an upper bound on the performance of superscalar processors exploiting basic control independence.  ... 
doi:10.1109/hpca.1999.744346 dblp:conf/hpca/RotenbergJS99 fatcat:ns45qyk5wzglnayipgcacseine

Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

P.W. Cook, M. Gupta, V. Zyuban, J. Wellman, A. Buyuktosunoglu, P.N. Kudva, H. Jacobson, S.E. Schuster, P. Bose, D.M. Brooks
2000 IEEE Micro  
We also postprocessed the performance simulation output and fed the average resource use statistics to the energy models to get the average power numbers.  ...  Here, we assume a generic, parameterized, out-of-order superscalar processor model adopted in a research simulator called Turandot. 12, 13 (Figure4is essen- Figure 5 . 5 Figure 5.  ...  Such models will enable designers to make the right choices in defining the future generation of energy-efficient microprocessors. MICRO  ... 
doi:10.1109/40.888701 fatcat:ppinuavlsjf2bouizu2yhbmonm

Statistical simulation: Adding efficiency to the computer designer's toolbox

L. Eeckhout, S. Nussbaum, J.E. Smith, K. De Bosschere
2003 IEEE Micro  
Similarly, for making system-level design decisions, where a processor (or several processors) might be combined with many other components, a very detailed simulation model is often unjustified or impractical  ...  Detailed models of register transfer activity typically conduct simulation at the microarchitecture level.  ...  of superscalar processors.  ... 
doi:10.1109/mm.2003.1240210 fatcat:nith3o67vvcrjlvxg77wvqyzh4

A Visual Simulation Framework For Simultaneous Multithreading Architectures

Adrian Florea, Alexandru Ratiu, Arpad Gellert, Lucian N. Vintan
2011 ECMS 2011 Proceedings edited by: T. Burczynski, J. Kolodziej, A. Byrski, M. Carvalho  
In order to understand and control this expansion, researchers need to design and implement larger and more complex systems' simulators.  ...  We introduce the SMTAHSim framework, an educational tool that simulates in an interactive manner the important aspects of this particular microarchitecture.  ...  The simulation is initialized via the Configuration Manager and is run via the Simulation Control module (step by step or full trace simulation).  ... 
doi:10.7148/2011-0403-0409 dblp:conf/ecms/FloreaRGV11 fatcat:ju5njgpyxbbgzhrwea5teffrla

ReSim, a trace-driven, reconfigurable ILP processor simulator

S. Fytraki, D. Pnevmatikatos
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
In our experiments with a 4-way superscalar processor ReSim achieves a simulation throughput of up to 28MIPS, and offers more than a factor of 5x improvement over the best reported ILP processor hardware  ...  In this paper we propose ReSim, a parameterizable ILP processor simulation acceleration engine based on reconfigurable hardware.  ...  It provides a range of simulation models ranging from fast, functional simulation up to a detailed timing simulator modeling the PowerPC processor micro-architectural state.  ... 
doi:10.1109/date.2009.5090722 dblp:conf/date/FytrakiP09 fatcat:7dev3xr7kva6tnf6h6qqxoc7kq

Accelerating Architectural Simulation Via Statistical Techniques: A Survey

Qi Guo, Tianshi Chen, Yunji Chen, Franz Franchetti
2016 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In computer architecture research and development, simulation is a powerful way of acquiring and predicting processor behaviors.  ...  Interestingly, we observe that most of these work are built upon statistical techniques.  ...  [104] further built a mechanistic analytical model for superscalar in-order processors.  ... 
doi:10.1109/tcad.2015.2481796 fatcat:jkrw5qd2irgj5cqdw6p4bewygq

An integrated performance and power model for superscalar processor designs

Yongxin Zhu, Weng-Fai Wong, Ştefan Andrei
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints.  ...  The model's performance and power results are in good agreement with detailed simulations, previous models and physically measured results.  ...  Validation via Maximum Total Power: The UltraSPARC-III processor [11] is a 4-way superscalar processor manufactured with a 0.13µm process and a V dd of 1.5 volts.  ... 
doi:10.1145/1120725.1120764 dblp:conf/aspdac/ZhuWA05 fatcat:wj5ai747dreptiqi6vnmvhm3ci

A mechanistic performance model for superscalar out-of-order processors

Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
2009 ACM Transactions on Computer Systems  
The mechanistic model is applied to the general problem of resource scaling in out-of-order superscalar processors.  ...  A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling.  ...  The average difference for the mechanistic interval model compared to simulation is 7% for a 4-wide superscalar out-of-order processor, and we found the model to be accurate across the processor design  ... 
doi:10.1145/1534909.1534910 fatcat:trmg3ixtendonbhwpm5wli4d5m

Superspeculative microarchitecture for beyond AD 2000

M.H. Lipasti, J.P. Shen
1997 Computer  
Weak-dependence model. Instead, we propose the weak-dependence model for superspeculative processors.  ...  We plan to develop simulation models of the prototype that can provide performance accuracy down to the machine cycle level.  ... 
doi:10.1109/2.612250 fatcat:ezukhsogtvcnjfga5hqpj5jcsi

A time-stamping algorithm for efficient performance estimation of superscalar processors

Gabriel Loh
2001 Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '01  
Fast and accurate methods for simulating program execution on realistic and hypothetical processor models are of great interest to many computer architects and compiler writers.  ...  The increasing complexity of modern superscalar microprocessors makes the evaluation of new designs and techniques much more difficult.  ...  This research was directly inspired by earlier work by Bradley Kuszmaul on using a time-stamping approach to measure the critical path of programs executing on a processor with a wraparound instruction  ... 
doi:10.1145/378420.378437 dblp:conf/sigmetrics/Loh01 fatcat:pihlcygze5frfoeo6n5fedcvbm

Challenges in processor modeling and validation [Guest Editors' introduction]

P. Bose, T.M. Conte, T.M. Austin
1999 IEEE Micro  
Thus, the modeling of EPIC/VLIW processors must put the compiler in the loop although traditional (superscalar) modeling does not. Speeding up the modeling of such processors poses new challenges.  ...  It is this model that is subjected to simulation-based architectural validation prior to actual tape-out of the processor.  ...  His research interests include high-performance computer architectures and performance modeling, verification, and application tuning.  ... 
doi:10.1109/mm.1999.768495 fatcat:jfxhc7zbsrhcrfdzr575xsnp2a
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