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Soft Error Rate Determination for Nanometer CMOS VLSI Logic

Fan Wang, Vishwani D. Agrawal
2008 Proceedings of the ... Annual Southeastern Symposium on System Theory  
In this paper we model neutron-induced soft errors using two parameters, namely, frequency and intensity.  ...  With this model we are able to accurately model electrical masking factors in logic circuits.  ...  Such probability can be obtained from existing computer programs, for example, IBM's SEMM (Soft Error Monte-Carlo Modeling) program [13] .  ... 
doi:10.1109/ssst.2008.4480247 fatcat:nox7aavrn5cfrmvx4gf3ssfo2m

Soft error resilience in Big Data kernels through modular analysis

Sui Chen, Greg Bronevetsky, Lu Peng, Bin Li, Xin Fu
2016 Journal of Supercomputing  
vulnerable to soft errors, understand how numerical errors propagate through the program, and apply fault resilience techniques effectively.  ...  ErrorSight achieves this through efficient generation of error profiles leveraging the predictive power of the Boosted Regression Tree model.  ...  We are also appreciative of the opportunity to be involved in and contribute to KULFI.  ... 
doi:10.1007/s11227-016-1682-2 fatcat:p66wey5hyjbk5mwj4o7xv776ly

SoftArch: an architecture-level tool for modeling and analyzing soft errors

X. Li, S.V. Adve, Pradip Bose, J.A. Rivers
2005 2005 International Conference on Dependable Systems and Networks (DSN'05)  
This paper proposes a model and tool, called Soft-Arch, to enable analysis of soft errors at the architecturelevel in modern processors.  ...  SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior architecture-level tools, SoftArch is more comprehensive or faster.  ...  or passing through logic. (2) A model for soft error propagation, which results in the propagation of generated errors to other values. (3) A definition of when an erroneous value contributes to processor  ... 
doi:10.1109/dsn.2005.88 dblp:conf/dsn/LiABR05 fatcat:n7zhrmy7djdixhsytn4mu6ajii

The Study of Transient Faults Propagation in Multithread Applications [article]

Navid Khoshavi, Armin Samiei
2016 arXiv   pre-print
In addition, a detail study of the impact of SEUs and MBUs on multithreaded programs will be presented in the Appendix.  ...  This work concentrates on leveraging the intrinsic soft-error-immunity feature of Spin-Transfer Torque RAM (STT-RAM) as an alternative for SRAM-based storage and operation components.  ...  However, the soft error in logic components still can be propagated in our proposed approach.  ... 
arXiv:1607.08523v1 fatcat:w3udglgjyneovkfcuanbucr2dq

Analyzing the Resilience of Convolutional Neural Networks Implemented on GPUs

Khalid Adam, Izzeldin I. Mohd, Younis Ibrahim
2021 International journal of electrical and computer engineering systems  
Thus, the generated fault may corrupt data values or logic operations and cause errors, such as Silent Data Corruption. unfortunately, soft errors propagate from the physical level (microarchitecture)  ...  However, GPUs are prone to soft errors. These errors can impact the behaviors of the GPU dramatically.  ...  Section 3 which is brief background of AlexNet, Graphics Processing Units, and Soft Errors Propagation in GPUs.  ... 
doi:10.32985/ijeces.12.2.4 fatcat:43lo77ew7jeylgfqferxhywnxm

Soft error propagation in floating-point programs

Sha Li, Xiaoming Li
2010 International Performance Computing and Communications Conference  
We first give the general modeling method we use to analyze soft error propagation.  ...  More specifically, we model the error propagation of soft error in the four basic arithmetic floating-point operations, and use simulation to build a quantitative and empirical predictor that can predict  ...  The first part is the error propagation for the four basic arithmetic operations; the second part is the error tolerance that is empirically computed from the simulation.  ... 
doi:10.1109/pccc.2010.5682305 dblp:conf/ipccc/LiL10 fatcat:dhfsyh6mfjaclixkfzqzekhacu

Clock skew scheduling for soft-error-tolerant sequential circuits

Kai-Chiang Wu, Diana Marculescu
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Soft errors have been a critical reliability concern in nanoscale integrated circuits, especially in sequential circuits where a latched error can be propagated for multiple clock cycles and affect more  ...  Experiments reveal that 30-40% reduction in the soft error rate for a wide range of benchmarks can be achieved.  ...  Clock Skew Scheduling Based on Piecewise Linear Programming The motivating example in Section 3 is a special case of CSS for MBU-aware soft error tolerance.  ... 
doi:10.1109/date.2010.5456956 dblp:conf/date/WuM10 fatcat:qoqvn3qzzrao7gupflaayyrdsm

A Model-Based Soft Errors Risks Minimization Approach

Muhammad Sheikh Sadi, D. G. Myers, Cesar Ortega Sanchez, Jan Jurjens
2009 2009 Fourth International Conference on Embedded and Multimedia Computing  
This improvement is achieved by presenting a criticality ranking (among the components) formed by combining a prediction of faults, consequences of them, and a propagation of errors at the system modeling  ...  phase; and pointing out ways to apply changes in the model to minimize the risk of degradation of desired functionalities.  ...  A soft error in C 1 (before it passes a second message) sees an increase in level of consequences in C 2 to s 1 x 2, since soft errors may propagate from C 1 to C 2 through the passed message.  ... 
doi:10.1109/em-com.2009.5402994 fatcat:4bussggfpfdmjjgrh6gnhwfoj4

IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults

Songjun Pan, Yu Hu, Xiaowei Li
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A structure's IVF is the probability an intermittent fault in that structure causes an external visible error (failure).  ...  Prior researches have proposed several metrics to analyze the vulnerability of microprocessor structures to soft errors and hard faults, however, the vulnerability of these structures to intermittent faults  ...  A structure's AVF is the probability that a soft error in it causes an external visible error.  ... 
doi:10.1109/tvlsi.2011.2134115 fatcat:nwbjz3giivduff736u4kdy2xc4

IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults

Songjun Pan, Yu Hu, Xiaowei Li
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
A structure's IVF is the probability an intermittent fault in that structure causes an external visible error (failure).  ...  Prior researches have proposed several metrics to analyze the vulnerability of microprocessor structures to soft errors and hard faults, however, the vulnerability of these structures to intermittent faults  ...  A structure's AVF is the probability that a soft error in it causes an external visible error.  ... 
doi:10.1109/date.2010.5457206 dblp:conf/date/PanHL10 fatcat:irh2nbuqpbfu7ctmfwqcqsgsia

A Soft Control Model for Human Reliability Analysis in APR-1400 Advanced Control Rooms (ACRs)

Jun Su Ha
2015 Procedia Engineering  
Considerations are provided for the soft control models developed to be used in HRAs.  ...  In this study, the soft control tasks are analyzed and modelled to be used for development of the basic human reliability data and quantification of human error probability.  ...  This taxonomy is used in this study to figure out the soft control error propagation.  ... 
doi:10.1016/j.proeng.2015.01.338 fatcat:sfnzo37uyfd2tb634jts6twb5q

Output remapping technique for critical paths soft-error rate reduction

Q. Ding, H. Yang, Y. Wang, H. Wang, R. Luo
2010 IET Computers & Digital Techniques  
Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead.  ...  As technology scales, soft errors in deep submicron circuits have become a major reliability concern due to smaller node capacitances and lower supply voltages.  ...  Sections 3 and 4 introduce our soft error analysis model including the generation and propagation model.  ... 
doi:10.1049/iet-cdt.2009.0038 fatcat:zg5bhfbplfhw5h5bngp7si45ua

A Selective Mitigation Technique of Soft Errors for DNN Models Used in Healthcare Applications: DenseNet201 Case Study

Khalid Adam, Izzeldin I. Mohd, Younis Ibrahim
2021 IEEE Access  
Then the reliability of the model under soft error propagation in GPU was evaluated.  ...  Therefore, this necessitates further studies, especially considering that the programming models used with GPU are very different, which can significantly influence the propagation of error in GPU-based  ...  His research interests include reliability of AI models through AI accelerators in safety-critical systems and accelerating deep learning models.  ... 
doi:10.1109/access.2021.3076716 fatcat:4abzjucsnncgbcqpfvu7lorwda

EBSCN: An Error Backtracking Method for Soft Errors Based on Clustering and a Neural Network

Nan Zhang, Jianjun Xu, Xiankai Meng, Qingping Tan
2019 IEEE Access  
The results showed that the proportion of the function in which the soft error actually occurs in the ranking of the top 25% of the suspiciousness sequence is no less than 82%, and the proportion ranked  ...  In this paper, we present EBSCN, an error backtracking method.  ...  Its own algorithm causes errors to propagate horizontally, whereas the function C that is subsequently executed causes errors to propagate vertically, such that the Algorithm 1 Sample Program Input: An  ... 
doi:10.1109/access.2019.2947005 fatcat:gdze52g6cbbdvbzvwurdl4yjsq

SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time

Michael Gschwind, Valentina Salapura, Catherine Trammell, Sally A. McKee
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
in increased soft error resilience; and (3) identify areas where microarchitectural data corruption can be tolerated as performance degradation without impact on correctness, yielding even greater soft  ...  Starting from design data for the entire processor, we extend the microprocessor verification methodology to study soft error propagation through microprocessor logic into the architected processor state  ...  error injection with Fusion and the FLite environment, and with model build.  ... 
doi:10.1109/iccd.2011.6081430 dblp:conf/iccd/GschwindSTM11 fatcat:dw7ovpsfwfbxvkejh6cso4tpc4
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