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SVtL: System Verification Through Logic Tool Support for Verifying Sliced Hierarchical Statecharts
[chapter]
2007
Lecture Notes in Computer Science
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Model checking object-based systems designed in UML necessitates the transformation of the statechart diagrams (describing the behavior of the objects) to a verification model. ...
It would thus be very useful to have a tool that automates this proces and allows the integration of a formal design method and verification of the model in an early phase of the development of the system ...
Model checking object-based systems designed in UML necessitates the transformation of the statechart diagrams (describing the behavior of the objects) to a verification model. ...
doi:10.1007/978-3-540-71998-4_9
fatcat:qwysce2p4vg27pfa23nraxxx7m
Design validation of embedded dependable systems
2001
IEEE Micro
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. • The evolution and verification of product and process designs. The quality of a product design depends on the quality of the process that produces it. ...
A common characteristic of such embedded systems is their increasing complexity in intrinsic terms-distribution management, redundancy, functionality layering, and so on-and of their in-the-field operation-environmental ...
Formal verification Formal verification is a hot topic especially for the development of dependable embedded systems. ...
doi:10.1109/40.958699
fatcat:wghik64werc27lhq3tyumg2xn4
Towards verified automotive software
2005
Software engineering notes
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Feasibility of this approach was validated on a case study that also showed how verification can be integrated into the development process. ...
For this purpose it introduces a verification approach, including a framework of verified modules which assists the verification of the actual application. ...
Manfred Broy at the Technische Universität München as well as Richard Bogenberger and David Trachtenherz at BMW Research. ...
doi:10.1145/1082983.1083199
fatcat:5zhsdmhlzzbv3eaislx4tm5eui
Ontology-Based Verification of UML Class Model XOR Constraint and Dependency Relationship Constraints
2021
Intelligent Automation and Soft Computing
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We use various UML class models to validate the proposed ontology-based method, easy and efficient transformation and verification of unsupported elements. ...
If a model has bugs, then MDE can transfer these to a new code. The class model is a key component of UML that is used in analysis and design. ...
This work focuses on the design and development of a rigorous method based on an ontology that facilitates transformation and verification of UML class model elements. ...
doi:10.32604/iasc.2021.015071
fatcat:usrcnysxkfftdfvylyhsdo5kb4
A Co-verification Method Based on TWCNP-OS for Two-way Cable Network SOC
2008
International Journal of Communications, Network and System Sciences
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Performance analysis of our current implementation and our experience with developing this system based on TWCNP-OS will be presented. ...
Most importantly, since the introduction of TWCNP-OS to our FPGA-based platform, we have observed increased productivity among high-level application developers who have little experience in FPGA application ...
The scientific verification method shortens the development cycle and the validated system is stable and can be applied in the verification of other embedded system. ...
doi:10.4236/ijcns.2008.12024
fatcat:orabpcqc6nbbxpz3k4barqdqtm
Semiformal Verification of Embedded Software in Medical Devices Considering Stringent Hardware Constraints
2009
2009 International Conference on Embedded Software and Systems
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In recent days, the complexity of software has increased significantly in embedded products in such a way that the verification of Embedded Software (ESW) now plays an important role to ensure the product's ...
This work proposes a semiformal verification approach that combines dynamic and static verification to stress and cover exhaustively the state space of the system. ...
Acknowledgement We thank Daniel Kroening for many helpful discussions about CBMC and SATABS model checking tools. ...
doi:10.1109/icess.2009.82
dblp:conf/icess/CordeiroFCM09
fatcat:wiuwzndkynglpfy6d6gaexg7ne
A taxonomy of grid workflow verification and validation
2008
Concurrency and Computation
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In a grid architecture, a grid workflow management system is a type of high-level grid middleware which is supposed to support modelling, redesign and execution of largescale sophisticated scientific and ...
As such, in this paper, we analyse the grid workflow verification and validation and present a taxonomy. ...
ACKNOWLEDGEMENTS A preliminary version of this paper appeared in AusGrid2006 [62] . ...
doi:10.1002/cpe.1220
fatcat:e3mgph2fkjgdlf3snqskb4wkzy
SysML Models Verification and Validation in an Industrial Context: Challenges and Experimentation
[chapter]
2018
Lecture Notes in Computer Science
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We highlight the work, requirements and benefits that arise from the appli-cation of existing technical solutions, and hint at new perspectives and future development in system verification and validation ...
This paper presents a solution for SysML model verification and validation, with a return of experience from its implementation in an industrial context. ...
This work is supported by Bombardier Transportation SAS and the ANRT CIFRE grant #2016/0262. ...
doi:10.1007/978-3-319-92997-2_9
fatcat:z4seeusf6fa6fidvzfrb7wo23e
Increasing and Validating the Safety and Reliability of Cyber-Physical Systems
2018
Zenodo
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Keywords: cyber-physical systems; safety and security; verification and validation; dependable systems engineering; model-based; automated test case generation; real-time monitoring ...
Examples include safe and secure reference architectures; methods for model-based analysis of safety-critical systems; automated test case generation; and real-time monitoring of complex systems. ...
Conclusion The tools and methodologies developed by AIT's Dependable Systems Engineering experts support the user in both, the system design as well as the system verification phases with innovative solutions ...
doi:10.5281/zenodo.1486559
fatcat:fyx7wqtsina3nczj5ickbyj3jy
A Unified Framework for Speaker and Utterance Verification
2019
Interspeech 2019
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Speaker and utterance verification are two tasks that co-exist in text-dependent speaker verification (SV), where a phrase of the same lexical information is spoken during train and test sessions. ...
The unified framework is based on long short term memory network trained using both speaker and utterance information. We use Part I of RSR2015 database for the studies in this work. ...
A1687b0033 from the Singapore Government's Research, Innovation and Enterprise 2020 plan (Advanced Manufacturing and Engineering domain). ...
doi:10.21437/interspeech.2019-1994
dblp:conf/interspeech/LiuMD019
fatcat:s5asxzcicjd7tneczhnkiih5vy
Framework for the Formal Specification and Verification of Security Guidelines
2018
Advances in Science, Technology and Engineering Systems
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In this paper, we present our approach that aims at integrating the formal specification and verification of security guidelines in early stages of the development lifecycle by combining both the model ...
We present our framework that is based on an extension of LTS (labelled transition Systems) by data dependence information to cover the end-to-end specification and verification of security guidelines. ...
Verification As previously mentioned, security guidelines will be modeled in the form of sequence of atomic propositions or statements representing the behavior of the system. ...
doi:10.25046/aj030106
fatcat:p6hdgic4nzak5mfbyhyhchfudi
Self-adaptive software needs quantitative verification at runtime
2012
Communications of the ACM
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The requirements of adaptiveness and dependability are traditionally the concern of different research communities, with researchers involved in autonomic computing developing adaptive software systems ...
model of the system based on observations of its behavior; for example, for the DTMC in Figure 4 , this component can update the service failure rates x, y, and z in line with the observed service behavior ...
doi:10.1145/2330667.2330686
fatcat:s75xkr5oejcr5cch27mezzm5my
Deep neural networks for small footprint text-dependent speaker verification
2014
2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
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In this paper we investigate the use of deep neural networks (DNNs) for a small footprint text-dependent speaker verification task. ...
Experimental results show the DNN based speaker verification system achieves good performance compared to a popular i-vector system on a small footprint text-dependent speaker verification task. ...
Acknowledgments The authors would like to thank our colleague Georg Heigold for help with training the DNN models. ...
doi:10.1109/icassp.2014.6854363
dblp:conf/icassp/VarianiLMMG14
fatcat:cnzzktyes5dd3fkakwgnwi2mbq
Development of Dependable Controllers in the Context of Machines Design
[chapter]
2014
Lecture Notes in Mechanical Engineering
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In order to achieve a dependable controller, some steps can be considered, such as the formalization of its specification -before being translated to the program that will be inserted in the controller ...
behavior of the Human Machine Interface of the Mechatronic system. ...
In this paper we report on results of work on mode-based verification resorting to partial models of the Plant. ...
doi:10.1007/978-3-319-05203-8_18
fatcat:f2ie73rtkng5jm3rpn3ko4fbse
Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems
[chapter]
2006
Lecture Notes in Computer Science
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First, we present the ALDERIS platform-independent visual language for component-based system development. Second, we demonstrate the use of the ALDERIS language on a helicopter autopilot DRE design. ...
Unlike most modeling languages, ALDERIS has formally defined semantics providing a way for the formal verification of dense real-time properties and energy consumption. ...
Models developed using ALDERIS can be verified and analyzed using the open-source DREAM tool available for download at http://dre.sourceforge.net. ...
doi:10.1007/11796435_8
fatcat:lgsnxy3fgnfkbcqr26cvzkkkiy
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