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An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation
[chapter]
2012
Lecture Notes in Computer Science
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Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). ...
In PA-DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. ...
by Community of Madrid. ...
doi:10.1007/978-3-642-29912-4_4
fatcat:szrmvqtlyfgatoc5c6iopwh57i
Early feedback on side-channel risks with accelerated toggle-counting
2009
2009 IEEE International Workshop on Hardware-Oriented Security and Trust
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Early detection of side-channel leakage in the design of a digital crypto-circuit is as important as getting the design functionally correct. ...
In this paper, we present a design method to provide early feedback on side-channel leakage based on toggle-counting. ...
Figure 4 shows a design flow for early feedback of the Side-Channel risks. ...
doi:10.1109/hst.2009.5224961
dblp:conf/host/ChenS09
fatcat:pthnc352ezcezowja7w7ad6tqa
A Feasibility Review for an Uneven Baseline Basis Minimal Ballast Ship
2020
한국해양공학회지
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In this study, the existing alternatives of ballast water are reviewed and a new design concept is studied on the basis of the existing bulk carrier hull form. ...
To check the performance feasibility of the new concept, ship resistance performance is reviewed based on a model scale ship resistance performance analysis. ...
Acknowledgements The initial concept of an 'uneven baseline minimal ballast water bulk carrier' was introduced as a proceeding at the 17th International
Congress on Maritime Transportation and Harvesting ...
doi:10.26748/ksoe.2019.111
fatcat:3t2tda5edrceljzw7rhdfokvoq
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
2011
2011 International Conference on Reconfigurable Computing and FPGAs
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In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. ...
, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. ...
Figure 2 . 2 EPE related imbalance of side channel traces in DPL logic. ...
doi:10.1109/reconfig.2011.3
dblp:conf/reconfig/HeTR11
fatcat:ie7hhhjhmrfjhdsgzlt7vuuofm
ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning
[article]
2022
arXiv
pre-print
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Such a method helps in reducing the computational complexity due to use of strong inversion model in client-side adversarial training as well as vulnerability of attacks launched in early training epochs ...
So we propose ResSFL, a Split Federated Learning Framework that is designed to be MI-resistant during training. ...
Cost Analysis The number of parameters and floating point operations (FLOPs) of different schemes are listed in Table 6 . ...
arXiv:2205.04007v1
fatcat:jzgxgfpclnan3oryd76vobotcu
Low-energy encryption for medical devices
2013
Proceedings of the 50th Annual Design Automation Conference on - DAC '13
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This paper will discuss the different abstraction layers and design methods applied to obtain low power/low energy and at the same time side-channel and fault attack resistant cryptographic implementations ...
Differently, while skipping one optimization step in a design for low energy or low power, merely reduces the battery life time, skipping a countermeasure, means opening the door for a possible attack. ...
In order to resist side-channel analysis, circuit-level countermeasures are crucial. ...
doi:10.1145/2463209.2488752
dblp:conf/dac/FanRRV13
fatcat:f4qeuxyc3jekncgbsqlcqhcsmu
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
[chapter]
2006
Lecture Notes in Computer Science
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Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. ...
Despite their benefits for security applications they have not been adapted to current mainstream designs due to the lack of electronic design automation support and their nonstandard or proprietary design ...
In a summary, differential dynamic well balanced gates seem to be the best choice to design secure hardware resistant to side-channel attacks. ...
doi:10.1007/11894063_31
fatcat:v7mshto3evbfrc55vgumhsqvvu
STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay
2017
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. ...
Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. ...
One of the most attractive solutions for hardware implementations is to use a secure logic style; this approach has the particular advantage that side channel resistance is built in at the lowest layer ...
doi:10.1109/isvlsi.2017.22
dblp:conf/isvlsi/KimHPV17
fatcat:zhdi7vmvlrekhlhguhhedekfri
Development Workflow for Manifolds and Fluid Components Based on Laser Powder Bed Fusion
2021
Applied Sciences
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The methodology aims to lead the designer from the specification of the task, through a step-by-step embodied design, to a technical and economic evaluation of the optimized, first-time manufactured part ...
At the same time, increased direct manufacturing costs are identified. ...
Acknowledgments: The authors gratefully acknowledge the help of Knorr-Bremse for providing the AM infrastructure and specifically Torsten Stickel for his contribution of product and development knowledge ...
doi:10.3390/app11167335
fatcat:qq66bocv6zcythfrqk7ct7gaxa
Urinalysis for diaper-wearing elderly people using a combination of cotton-based diagnostic devices and smartphone-based image analysis
2019
Health Technology
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Acknowledgments Funding: The study was supported by project 'MOST 108-2745-8-007-001' of Ministry of Science and Technology, Taiwan. ...
In 2010, the direct and indirect costs of UTI in the United States amounted to approximately $2.3 billion (2) . The incidence of UTI in women is far higher than in men. ...
The entire procedure is completed in a single step.
Results To evaluate the performance of urine test device to detect nitrite, we spotted serially diluted nitrite onto each test zone. ...
doi:10.21037/ht.2019.08.02
fatcat:lk4x5fxuo5drbjangbneem6sqi
Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present
2021
Journal of Integrated Circuits and Systems
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In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. ...
Since its invention, power analysis attacks are a threat to the security of such circuits. ...
ACKNOWLEDGEMENTS This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior -Brasil (CAPES) -Finance Code 001. ...
doi:10.29292/jics.v16i2.501
fatcat:y4zvlpnujrdchnjcmfm7ivif7m
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs
[chapter]
2017
Lecture Notes in Computer Science
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Different cost functions for the placement are tested and evaluated w.r.t. the resulting side-channel resistance on a Spartan-6 FPGA. ...
As most of the DPA-resistant logic is based on dual-rails, properly implementing them is a challenging task on FPGAs which is due to their fixed architecture and missing freedom in the design tools. ...
Conclusion In this work we have shown that verifying DRP logics on FPGAs only by a power-based side-channel analysis is insufficient. ...
doi:10.1007/978-3-319-66787-4_20
fatcat:adufrmefq5d6fmb7p6xn5jtzpm
Combinatorial Logic Circuitry as Means to Protect Low Cost Devices Against Side Channel Attacks
[chapter]
2007
Lecture Notes in Computer Science
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The physical properties and the use of standard CMOS technology ensure extremely low additional production cost. ...
Thus, our approach is very well suited to improve the security of low cost devices such as wireless sensor nodes. ...
Acknowledgement This work was partially funded by the German Ministry of Education and Research under grant 01AK060B. ...
doi:10.1007/978-3-540-72354-7_20
fatcat:liwikaf3azbk5gpnfw65qr74wm
High speed test interface module using MEMS technology
2015
Microelectronics and reliability
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The process is complete and samples are packaged at this step.
Released Device [113]. 116 ____________________________________ ...
115
Release Process Before the final release, the wafers are diced into individual dies. The sacrificial lay is then removed using oxygen plasma dry-etch process. ...
A valuable indicator to evaluate the significance of test and fault detection at early stages in the VLSI industry is the rule of ten. ...
doi:10.1016/j.microrel.2014.11.010
fatcat:hela63ims5fxjeu4df3ylumex4
Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box
[chapter]
2011
Lecture Notes in Computer Science
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In a recent work from Eurocrypt 2011, Renauld et al. discussed the impact of the increased variability in nanoscale CMOS devices on their evaluation against side-channel attacks. ...
Next, we evaluate the side-channel leakages of these S-boxes, using both simulations and actual measurements. ...
Such a design choice has clear advantages in terms of area cost, but potentially implies more side-channel leakage. ...
doi:10.1007/978-3-642-23951-9_15
fatcat:t2xxwhyo4jcbjdis4tkybvzj6m
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