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An Enhanced Algorithm for Memory Systematic Faults Detection in Multicore Architectures Suitable for Mixed-Critical Automotive Applications

Abdullah El-Bayoumi
2020 International Journal of Safety and Security Engineering  
Evolution to multicore architectures has been trending, as a result of the shift towards the nanoscale semiconductor industry.  ...  The proposed safety mechanisms have been investigated and evaluated for Aurix Tri-core and Renesas RH850 targets with lots of suggestions to have a fully compliant architecture with principles and methods  ...  ACKNOWLEDGMENT The work presented here has been partially carried out for the framework of autonomous driving applications architectures, which are supported by the Research and Development Center of Valeo  ... 
doi:10.18280/ijsse.100405 fatcat:l7lethnjn5fdjosjnygfaer5gu

Secure Lightweight Entity Authentication with Strong PUFs: Mission Impossible? [chapter]

Jeroen Delvaux, Dawu Gu, Dries Schellekens, Ingrid Verbauwhede
2014 Lecture Notes in Computer Science  
To such an extent, that we cannot support the use of any proposal in its current form. All proposals aim to compensate the lack of cryptographic properties of the strong PUF.  ...  The novelty of our work is threefold. First, we employ a unified notation and framework for ease of understanding.  ...  Tokens typically store a secret key in non-volatile memory (NVM), using a mature technology such as EEPROM and its successor Flash, battery-backed SRAM or fuses.  ... 
doi:10.1007/978-3-662-44709-3_25 fatcat:mm2m6qliljaxpepgs5nnzpiqki

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key

Hyungil Woo, Seokjun Jang, Sungho Kang
2021 IEEE Access  
In this paper, we propose a secure scan architecture using a skew-based lock and key to enhance the security of the scan design while maintaining the debuggability of the scan dump.  ...  INDEX TERMS Secure scan architecture, secure scan dump, skew-based lock and key, lock and key.  ...  Therefore, the attacker cannot identify the location of other key bits. 6) MEMORY ATTACK For countermeasures using its key value in NVMs can be vulnerable for the attack targeting the memory.  ... 
doi:10.1109/access.2021.3097348 fatcat:nhducotmbbfy3dtzoqikqehwga

Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation

G M Sridevi, Ashoka D V, B V Ajay Prakash
2022 Karbala International Journal of Modern Science  
A memory window is then created and adjusted for obtaining an optimal power flow with lesser data loss. The performance of the proposed design is evaluated using different performance measures.  ...  Transfer characteristics of the current are analysed based on the pseudo differential pair for proficient memory utilization.  ...  Unbounded Hardware Transactional Memory (UHTM) system was proposed based on the hybrid combination of DRAM and Non-Volatile Memory (NVM) [29] .  ... 
doi:10.33640/2405-609x.3223 fatcat:i2balt5mzfgfngn4wwc3m7gr7q

Phase-change memory

Omer Zilberberg, Shlomo Weiss, Sivan Toledo
2013 ACM Computing Surveys  
This article surveys the current state of phase-change memory (PCM) as a nonvolatile memory technology set to replace flash and DRAM in modern computerized systems.  ...  These allow PCM to stand on its own as a replacement for DRAM as main memory. Designs for hybrid memory systems with both PCM and DRAM are also shown and some designs for SSDs incorporating PCM.  ...  For example, a 16-line memory page incurs a 4-bit register to hold its shifting value. Some random number generator is used to supply an initial value for the cyclic shift when the page is replaced.  ... 
doi:10.1145/2480741.2480746 fatcat:lvyy3ibbuvaszdk3wazh2tiowy

Security Analysis of PUF-based Key Generation and Entity Authentication

Jeroen Delvaux
2017 Zenodo  
., true random number generators (TRNGs), cryptographic algorithms, error-correcting codes, non-volatile memory (NVM), etc.  ...  Numerous newly revealed flaws and attacks are presented throughout this thesis. On the bright side, the lessons learned can help improve the quality of future PUF-based systems.  ...  We filled in the blanks to the best of our insights and exclude this part from cryptanalysis. Moreover, the authors do not suggest the use of a particular strong PUF.  ... 
doi:10.5281/zenodo.2643392 fatcat:2pcr7p76qjbtnh36fuxsdk7enq

From Cryptography to Logic Locking: A Survey on The Architecture Evolution of Secure Scan Chains

Kimia Z Azar, Hadi M Kamali, Houman Homayoun, Avesta Sasan
2021 IEEE Access  
We evaluate all secure scan chain architectures in terms of security and resiliency, testability/debugging time and complexity, and area/power/delay overhead.  ...  Then, we provide a holistic overview of all secure scan chain architectures starting from preliminary methods introduced when cryptography is in place and the adversary threat model is very limited.  ...  (d = 2) Shift-in the Leaky Condition (d-bit Reverse-Shifted) based on d=2. Shift all FFs, Including SCs and SFFs, in Mode M 2 , to Put the k i into the LC.  ... 
doi:10.1109/access.2021.3080257 fatcat:tg7fcofqenb6dakqiwlt3q3kd4

Robust High-dimensional Memory-augmented Neural Networks [article]

Geethan Karunaratne, Manuel Schmuck, Manuel Le Gallo, Giovanni Cherubini, Luca Benini, Abu Sebastian, Abbas Rahimi
2021 arXiv   pre-print
Access to this explicit memory, however, occurs via soft read and write operations involving every individual memory entry, resulting in a bottleneck when implemented using the conventional von Neumann  ...  Experimental results demonstrate the efficacy of our approach on few-shot image classification tasks on the Omniglot dataset using more than 256,000 phase-change memory devices.  ...  ACKNOWLEDGEMENTS This work was partially funded by the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement number 682675).  ... 
arXiv:2010.01939v2 fatcat:ldjmz2hybvfbjboyrbsrwzsana

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery [article]

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
2018 arXiv   pre-print
cell sensing; (3) error correction using state-of-the-art algorithms and methods; and (4) data recovery when error correction fails.  ...  We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques.  ...  This work was also partially supported by ETH Zürich, the Intel Science and Technology  ... 
arXiv:1711.11427v2 fatcat:rvnbeg4eevfa7lczf2h2ificxi

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic [article]

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020 arXiv   pre-print
In this paper, we assess the security and testability of the state-of-the-art design-for-security (DFS) architectures in the presence of scan-chain locking/obfuscation, a group of solution that has previously  ...  Also, we demonstrate that the state-of-the-art DFS architectures impose some substantial architectural drawbacks that moderately affect both test flow and design constraints.  ...  Using a very wide memory to derive thousands of keys is quite demanding in terms of area, and it imposes higher complexity during PnR.  ... 
arXiv:2005.04262v1 fatcat:7pqucqnch5dm3ibkby5i6oqaw4

Architectural Techniques for Improving NAND Flash Memory Reliability [article]

Yixin Luo
2018 arXiv   pre-print
Raw bit errors are common in NAND flash memory and will increase in the future. These errors reduce flash reliability and limit the lifetime of a flash memory device.  ...  We show that NAND flash memory reliability can be improved at low cost and with low performance overhead by deploying various architectural techniques that are aware of higher-level application behavior  ...  In the next iteration, the min-sum algorithm uses the updated LLR values from the current iteration to identify the next set of bits that are most likely incorrect and need to be flipped.  ... 
arXiv:1808.04016v1 fatcat:fotned4yajc2xmaoezwjdrgypu

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Andreas Engel, Andreas Koch, Thomas Siebel
2015 2015 IEEE 40th Local Computer Networks Conference Workshops (LCN Workshops)  
A Structural Health Monitoring (SHM) application is used for the system level evaluation of the HaLoMote concept.  ...  The functionality of the overall WSN-based SHM system is shown with a laboratory-scale demonstrator.  ...  To avoid the fragmentation of the data structure storing the trigger events, a shift register based queue is used.  ... 
doi:10.1109/lcnw.2015.7365908 dblp:conf/lcn/EngelKS15 fatcat:cugvo6duqzgw3lwutiowjjda7m

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Wang, Z., +, TCAD March 2020 640-653 A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory.  ...  ., +, TCAD Sept. 2020 1935-1948 Data compression A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory.  ...  ., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS. Choi, Y., +, TCAD Dec. 2020 4828-4841 High-Level Synthesis Design Space Exploration: Past, Present, and Future.  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2021 2021 IEEE International Test Conference (ITC)  
waste of test time and resources; 2) Our DAT approach results in more accurate fault models which reflect the physical defects, thus ensuring high-quality tests at minimal cost.  ...  We first investigate the manufacturing process of STT-MRAM and physical defects that may take place in each step based on literature survey and silicon measurements.  ...  ACKNOWLEDGEMENTS ACKNOWLEDGEMENTS friends, and professors. Bowen, it is my luck to be your friend. We shared some amazing Acknowledgements xi  ... 
doi:10.1109/itc50571.2021.00022 fatcat:4hlsp34pcrgexkssoxu5m5c25a

A Survey of Machine Learning Applied to Computer Architecture Design [article]

Drew D. Penney, Lizhong Chen
2019 arXiv   pre-print
Notably, machine learning based strategies often surpass prior state-of-the-art analytical, heuristic, and human-expert approaches.  ...  The paper further analyzes current practice to highlight useful design strategies and identify areas for future work, based on optimized implementation strategies, opportune extensions to existing work  ...  They used k-means to cluster flip-flops during physical layout, minimizing clock wirelength at the expense of signal wirelength, noting that clock networks can consume more than 40% of chip power.  ... 
arXiv:1909.12373v1 fatcat:o4nscgkjfbes7kqwmtjvvgl3oa
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