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An Effective Technique to Higher Throughput for Streaming Applications on an MPSoC

Hassan Salamy
2019 Journal of Computers  
Embedded systems often employ a multi-processor system-on-a-chip (MPSoC) to enhance performance.  ...  The proposed technique is implemented and tested on real and hypothetical systems on a range of benchmarks and the results show the great improvement in the systems' throughput generated from the presented  ...  Multi-processor system-on-a-chip (MPSoC) is a computing architecture that utilizes multiple processing elements (possibly heterogeneous), a memory hierarchy, and a communication platform optimized for  ... 
doi:10.17706/jcp.14.8.507-518 fatcat:6dxf2os3hvccnfxkhu7iqsptyu

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo
2013 IEEE Journal of Solid-State Circuits  
A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams.  ...  In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous  ...  SYSTEM ARCHITECTURE The proposed processor is based on a heterogeneous multi-core architecture for low-power real-time object recognition in a mobile vision system [15] .  ... 
doi:10.1109/jssc.2012.2220651 fatcat:uh4ec3i64vdmjdev5sgck7iv2i

Cache-Aware Utilization Control for Energy Efficiency in Multi-Core Real-Time Systems

Xing Fu, Khairul Kabir, Xiaorui Wang
2011 2011 23rd Euromicro Conference on Real-Time Systems  
Multi-core processors are anticipated to become a major development platform for real-time systems.  ...  In this paper, we propose a twolevel utilization control solution for energy efficiency in multicore real-time systems.  ...  INTRODUCTION In recent years, more and more real-time systems are developed based on multi-core processors.  ... 
doi:10.1109/ecrts.2011.18 dblp:conf/ecrts/FuKW11 fatcat:7nvh7iziyzfnbjk2tkisniapx4

Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures

Hassan Salamy
2018 International Journal of Computer Applications  
As the complexity of embedded applications is ever increasing, the trend in embedded architecture is to utilize a multi-processor system on a chip (MPSoC).  ...  Then this article presents an effective task scheduler that integrates scheduling and on-chip scratchpad memory partitioning for the maximum optimization of the system.  ...  a single chip.  ... 
doi:10.5120/ijca2018917834 fatcat:byaxwwz3gnhgnecwpzfihrfy7m

Exploring locking & partitioning for predictable shared caches on multi-cores

Vivy Suhendra, Tulika Mitra
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Multi-core architectures consisting of multiple processing cores on a chip have become increasingly prevalent.  ...  This paper proposes the use of shared cache in a predictable manner through a combination of locking and partitioning mechanisms.  ...  CONCLUSION In this paper, we have explored predictable caching schemes for shared memory multi-cores in the context of preemptive hard real-time systems.  ... 
doi:10.1145/1391469.1391545 dblp:conf/dac/SuhendraM08 fatcat:kie4bdbtabhlvaoq32oidjcrx4

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Hassan Salamy, Olalekan Sopeju
2014 International Journal of Computer Applications  
As the utilization of multiprocessors system-on-chip (MPSoC) is becoming ubiquitous, demands for effective allocation and scheduling techniques are needed more than ever to harness the power of MPSoCs.  ...  An MPSoC is a system consisting of multiple heterogeneous processing cores, memory hierarchies, and communication infrastructure to effectively overcome the power and clock constraints from single core  ...  But due to their limited size in embedded systems, many multi-processors systems-on-chip use some kind of a memory hierarchy with small capacity but fast on-chip memories and large capacity slower offchip  ... 
doi:10.5120/17040-7350 fatcat:xi2bxvyg2zavzjhzbpxnovv47y

Implementation of Cache Fair Thread Scheduling for multi core processors using wait free data structures in cloud computing applications

A.S. Radhamani, E. Baburaj
2011 2011 World Congress on Information and Communication Technologies  
The primary goal of scheduling framework is to improve application throughput and overall system utilization in cloud applications.  ...  In this paper an effective scheduling framework for multi-core processors that strike a balance between control over the system and an effective network traffic control mechanism for high-performance computing  ...  A multi-core processor is a processing system composed of two or more individual processors, called cores, integrated onto a single chip package.  ... 
doi:10.1109/wict.2011.6141313 fatcat:awglbzxx3bay3fn5d7atbof3lm

Towards migrating legacy real-time systems to multi-core platforms

Farhang Nemati, Johan Kraft, Thomas Nolte
2008 2008 IEEE International Conference on Emerging Technologies and Factory Automation  
Developers of embedded real-time systems however hesitates a shift to multi-core processors, especially for existing "legacy" systems which have been developed with single-core processor assumptions.  ...  In this paper we investigate challenges of migrating complex legacy real-time systems to multi-core architectures. We propose componentization and partitioning to prepare the migration.  ...  Multi-Core Architectures A multi-core processor is a combination of two or more independent cores on a single chip. They are connected to a single shared memory via shared bus.  ... 
doi:10.1109/etfa.2008.4638477 dblp:conf/etfa/NematiKN08 fatcat:r4yjlh5ezbdi5epeoymucmgtei

Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs

Unmesh D. Bordoloi, Bharath Suri, Swaroop Nunna, Samarjit Chakraborty, Petru Eles, Zebo Peng
2012 2012 25th International Conference on VLSI Design  
Our CUDA implementation is devised to maximize the achievable speedups by various optimizations like exploiting on-chip shared memory and register usage.  ...  As such, existing tools to customize instruction sets of extensible processors rely on approximation methods or heuristics.  ...  PROBLEM DESCRIPTION In this section, we discuss our system model and formally present the multi-objective optimization problem. System Model: We assume a multi-tasking hard real-time system.  ... 
doi:10.1109/vlsid.2012.107 dblp:conf/vlsid/BordoloiSNCEP12 fatcat:yg3wx23zszbh5jjeeigtktyyky

A Novel Approach to Multiagent based Scheduling for Multicore Architecture

G. Muneeswari, A.Sobitha Ahila, Dr.K.L. Shunmuganathan
2011 GSTF International Journal on Computing  
This multiagent based scheduling algorithm promises in minimizing the average waiting time of the processes in the centralized queue and also reduces the task of the scheduler.  ...  In a Multicore architecture, each package consists of large number of processors. This increase in processor core brings new evolution in parallel computing.  ...  The research on the design and implementation of a cache-aware multicore real-time scheduler [3] discusses the memory limitations for real time systems.  ... 
doi:10.5176/2010-2283_1.2.58 fatcat:e2cqiloj4jaxtcti6vu5etdyj4

Real-Time power management for a multi-performance processor

Tohru Ishihara
2009 2009 International SoC Design Conference (ISOCC)  
The processor consists of multiple same-ISA PE (processing element) cores and a selective set-associative cache memory. The PE-cores differ in their clock speeds and energy consumptions.  ...  Our processor makes it possible to use the DVS control in embedded real-time systems and to perform more sophisticated dynamic power management.  ...  ACKNOWLEDGMENT This work is supported by Toshiba and VDEC, the Univ. of Tokyo with the collaboration of Renesas Technology, STARC, Panasonic, NEC Electronics, Toshiba, Synopsys, Cadence Design Systems  ... 
doi:10.1109/socdc.2009.5423892 fatcat:6ft7p6nkb5b4pfb75hmolz3rpa

HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems

Mario Günzel, Christian Hakert, Kuan-Hsun Chen, Jian-Jia Chen
2021 ACM Transactions on Embedded Computing Systems  
In this work, we consider real-time systems with hybrid shared-memory architectures, which consist of shared volatile memory (VM) and non-volatile memory (NVM).  ...  For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced.  ...  This device features a single computing core, integrated on-chip SRAM and on-chip FRAM as the non-volatile memory.  ... 
doi:10.1145/3477019 fatcat:dxo4bk63prc75dsqqxiu6eyk4a

Performance-controllable shared cache architecture for multi-core soft real-time systems

Myoungjun Lee, Soontae Kim
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
Multi-core processors with shared L2 caches can improve performance and integrate several functions of real-time systems on a single chip.  ...  However, tasks running on different cores increase interferences in the shared L2 cache, resulting in more deadline misses and, consequently, worse quality of real-time tasks.  ...  In addition, multi-core processors can reduce form factors and costs of real-time systems by integrating multiple tasks on a single chip and running them simultaneously on different cores.  ... 
doi:10.1109/iccd.2013.6657097 dblp:conf/iccd/LeeK13 fatcat:apsypeovt5epxkh2kfr754zbaa

System-Wide Energy Optimization for Multiple DVS Components and Real-Time Tasks

Heechul Yun, Po-Liang Wu, Anshu Arya, Tarek Abdelzaher, Cheolgi Kim, Lui Sha
2010 2010 22nd Euromicro Conference on Real-Time Systems  
In this work, we propose a realistic energy model considering multiple components with individually adjustable frequencies such as CPU, system bus and memory, and related task set characteristics.  ...  When considering multiple components, energy optimal frequencies depend on task set characteristics such as the number of CPU and memory access cycles.  ...  Findings and opinions expressed in this work are those of the authors and not necessarily those of the funding agencies.  ... 
doi:10.1109/ecrts.2010.14 dblp:conf/ecrts/YunWAAKS10 fatcat:uhabduvt4fd4fhzvzkoofp6bku

System-wide energy optimization for multiple DVS components and real-time tasks

Heechul Yun, Po-Liang Wu, Anshu Arya, Cheolgi Kim, Tarek Abdelzaher, Lui Sha
2011 Real-time systems  
In this work, we propose a realistic energy model considering multiple components with individually adjustable frequencies such as CPU, system bus and memory, and related task set characteristics.  ...  When considering multiple components, energy optimal frequencies depend on task set characteristics such as the number of CPU and memory access cycles.  ...  Findings and opinions expressed in this work are those of the authors and not necessarily those of the funding agencies.  ... 
doi:10.1007/s11241-011-9125-x fatcat:me4ikqtdubh4haxjtmull3zgfa
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