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Minimizing Delay in Shared Pipelines

Ori Rottenstreich, Isaac Keslassy, Yoram Revah, Aviran Kadosh
2013 2013 IEEE 21st Annual Symposium on High-Performance Interconnects  
In this paper, we study pipeline sharing, such that a single pipeline can be used to serve several packet types.  ...  Pipeline sharing decreases the needed total number of cores, but typically increases pipeline lengths and therefore packet delays.  ...  Therefore, while pipeline sharing decreases the needed number of cores, it can also increase the packet delay. Fig. 1(b) illustrates this pipeline sharing.  ... 
doi:10.1109/hoti.2013.10 dblp:conf/hoti/RottenstreichKRK13 fatcat:qlaiwy3zsvbbtpn7epfomqvmpe

High Throughput Multipliers Using Delay Equalization

Alka Raj, N. Kayalvizhi
2010 International Journal of Computer Applications  
In wave pipelined system the clock period should be greater than the difference between maximum delay and minimum delay + clocking overheads such as setup time, hold time, etc.  ...  Clock period can be reduced by minimizing the difference between maximum and minimum delay, i.e delay equalization has to be done.  ...  AREA MINIMIZATION To further decrease the delay elements added use delay element sharing and delay element shifting along with this so that area can be minimized Delay Element Sharing Delay element sharing  ... 
doi:10.5120/661-929 fatcat:u2j3rhlf2bdjlh5ygny2eojx2y

Minimizing the number of delay buffers in the synchronization of pipelined systems

X. Hu, R. G. Harber, S. C. Bass
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
Obviously. it would be beneficial to determine the minimum number of total delay buffer stages necessary to s)mchronize a pipelined system, so that the system hardware cost and complexity can be reduced  ...  In this paper. we present an algorithm to solve this buffer minimization problem. We will show that it can be recast in term of the clarsical minimum cost network flow problem.  ...  Minimizing the total delay buffer length As stated in the introduction, delay buffers may need to be introduced in order to synchronize the data paths within a pipelined system.  ... 
doi:10.1145/127601.127765 dblp:conf/dac/HuHB91 fatcat:yjpquh6a3jgy7ohqhpyfxo2wfm

Minimizing the number of delay buffers in the synchronization of pipelined systems

Xiaobo Hu, S.C. Bass, R.G. Harber
1994 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Obviously. it would be beneficial to determine the minimum number of total delay buffer stages necessary to s)mchronize a pipelined system, so that the system hardware cost and complexity can be reduced  ...  In this paper. we present an algorithm to solve this buffer minimization problem. We will show that it can be recast in term of the clarsical minimum cost network flow problem.  ...  Minimizing the total delay buffer length As stated in the introduction, delay buffers may need to be introduced in order to synchronize the data paths within a pipelined system.  ... 
doi:10.1109/43.331401 fatcat:sa3dmmdsvzcd7gfsexrb3xmh6u

Buffer assignment algorithms on data driven ASICs

M. Chatterjee, S. Banerjee, D.K. Pradhan
2000 IEEE transactions on computers  
By exploiting the inherent parallelism in the application, these architectures can maximize pipelining.  ...  A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wave-pipelining in digital systems under certain restrictions.  ...  ACKNOWLEDGMENTS This work was supported in part by U.S. National Science Foundation grant 9406946.  ... 
doi:10.1109/12.822561 fatcat:uzafsm233falhn33lzadjgkk7y

Energy minimization using multiple supply voltages

Jui-Ming Chang, M. Pedram
1997 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths.  ...  The scheduling problem refers to the assignment of a supply voltage level (selected from a fixed and known number of voltage levels) to each operation in a data flow graph so as to minimize the average  ...  Module Sharing After Scheduling Our goal is to minimize the resources after the scheduling has been done. The problem can be formulated as a minimal coloring of a circular arc graph [17] .  ... 
doi:10.1109/92.645070 fatcat:oq4cppm2ergrpos5vobrbuvn54

Architecture-level synthesis for automatic interconnect pipelining

Jason Cong, Yiping Fan, Zhiru Zhang
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
We formulate a novel global interconnect sharing problem for global wiring minimization and show that it is polynomial time solvable by transformation to a special case of the real-time scheduling problem  ...  In this paper we present an architecture-level synthesis solution to support automatic pipelining of on-chip interconnects.  ...  In addition, more data transfers can share the same global wire, as the minimal launch interval is reduced from K to 1.  ... 
doi:10.1145/996566.996731 dblp:conf/dac/CongFZ04 fatcat:u4gmoclngfcn5fynv3yhrtvera

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai
2012 Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design - ISLPED '12  
In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.  ...  We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty.  ...  Acknowledgment This work is supported in part by grants from National Science Foundation under CNS-0834599, CSR-0834599, CPS-0931931, and CCF-0903427, a contract from Semiconductor Research Cooperation  ... 
doi:10.1145/2333660.2333675 dblp:conf/islped/YinZHSZ12 fatcat:rpivyktfdjbyfar3hindo4n7cy

Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design

Hai Lin, Yunsi Fei
2009 2009 IEEE International Conference on Computer Design  
We demonstrate that different resource sharing schemes would affect both the hardware overhead and datapath delay of the custom instructions.  ...  In this paper, we introduce a pipelined configurable hardware structure for the hardware extension in ASIPs, so that structural hazards can be remedied.  ...  The coefficient α is set to 1, 0.5, 0 to represent three different cases, i.e., considering the area reduction only, area and delay trade-off, and minimizing the cycle delay for each custom instruction  ... 
doi:10.1109/iccd.2009.5413161 dblp:conf/iccd/LinF09 fatcat:zttojgsq2nb5djoo3udjw5lt7y

Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design

Hai Lin, Yunsi Fei
2012 ACM Transactions on Design Automation of Electronic Systems  
We demonstrate that different resource sharing schemes would affect both the hardware overhead and datapath delay of the custom instructions.  ...  In this paper, we introduce a pipelined configurable hardware structure for the hardware extension in ASIPs, so that structural hazards can be remedied.  ...  The coefficient α is set to 1, 0.5, 0 to represent three different cases, i.e., considering the area reduction only, area and delay trade-off, and minimizing the cycle delay for each custom instruction  ... 
doi:10.1145/2348839.2348843 fatcat:j2o5u43j3nc2bns5bnvyvc32iq

A Single Amplifier-Based 12-bit 100MS/s 1V 19mW 0.13µm CMOS ADC with Various Power and Area Minimized Circuit Techniques

Byeong-Woo KOO, Seung-Jae PARK, Gil-Cho AHN, Seung-Hoon LEE
2011 IEICE transactions on electronics  
This work describes a 12-bit 100 MS/s 0.13 µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area.  ...  The prototype ADC in a 0.13 µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively.  ...  A bit overlapped switching clock phase for signal selection switches minimizes an output signal settling delay, as observed in the conventional switched opamp sharing technique [13] .  ... 
doi:10.1587/transele.e94.c.1282 fatcat:dukodqe65ja7fklrujyte7xsci

Resource sharing in pipelined CDFG synthesis

Somsubhra Mondal, Seda Öǧrenci Memik
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
In this paper, we propose resource sharing techniques that can be incorporated into an automated synthesis flow to generate pipelined designs.  ...  Specifically, we propose an optimal algorithm for Constant-Slack Resource Sharing and a heuristic for the general Intra-Pipeline Stage Resource Sharing.  ...  Minimizing the resource requirement for these modules will then be equivalent to minimizing the overall resource demand for a given resource type in that pipeline stage.  ... 
doi:10.1145/1120725.1121019 dblp:conf/aspdac/MondalM05 fatcat:7r2dbz7n45aghj2lfenizw3nli

RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors

C. Akturan, M.F. Jacome
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
RS-FDRA can also minimize the increase in "register pressure" typically incurred by software pipelining.  ...  This ability is critical since, the need to insert spill code may result in significant performance degradation.  ...  In order to reduce register pressure in an SCC's schedule, we favor the retiming solutions that have larger delays on the edges associated with shared data objects, thus reducing the delays on the remaining  ... 
doi:10.1109/tcad.2002.804373 fatcat:lgb4bpunurbm3dlmqkilupdyg4

RS-FDRA

Cagdas Akturan, Margarida F. Jacome
2001 Proceedings of the ninth international symposium on Hardware/software codesign - CODES '01  
RS-FDRA can also minimize the increase in "register pressure" typically incurred by software pipelining.  ...  This ability is critical since, the need to insert spill code may result in significant performance degradation.  ...  In order to reduce register pressure in an SCC's schedule, we favor the retiming solutions that have larger delays on the edges associated with shared data objects, thus reducing the delays on the remaining  ... 
doi:10.1145/371636.371681 dblp:conf/codes/AkturanJ01 fatcat:m6rj7xaqzjbrhcnltu4xczw5my

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

Yen-Chuan Huang, Tai-Cheng Lee
2010 2010 IEEE International Solid-State Circuits Conference - (ISSCC)  
To maintain the characteristics of Nyquist sampling in this work, the input signal paths are carefully designed and simulated on the circuit and layout-level to minimize the input delay mismatch seen between  ...  As shown in Fig. 16 .5.1, an opamp can be shared by two adjacent stages due to the two-phase operation nature in a pipelined ADC.  ...  Acknowledgement: This work was supported by Mediatek, and the authors would like to thank TSMC for the support in chip fabrication.  ... 
doi:10.1109/isscc.2010.5433927 dblp:conf/isscc/HuangL10 fatcat:2vrnxwknwjgdzdmmdbnoobnm7a
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