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Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2018 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)  
ACKNOWLEDGMENTS The presented research effort is partially supported by the European Community Horizon 2020 programme under grant no. 688540 (UniServer) and grant no. 732631 (OPRECOMP).  ...  The combination of path shaping and operand bit-width truncation in the 32, 44 and 48 LSBs reduces these failures by 6.24×, 146.48× and 263.28× on average, respectively when compared to the original design  ...  Contributions and Outline The primary aim of this paper is to minimize the potential timing failures in a pipelined design by appropriately redesigning the target circuit for limiting the failure-prone  ... 
doi:10.1109/iolts.2018.8474084 dblp:conf/iolts/TsiokanosMNK18 fatcat:jhcwmxtbfvb6lok4abvztnwpwe

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

K Kunaparaju, S Narasimhan, S Bhunia
2011 2011 24th Internatioal Conference on VLSI Design  
Consequently, truncation of operand width in these data paths post-manufacturing can be used to tolerate delay failures. Truncating the input bits, however, affects the output quality.  ...  assignment, and number of critical paths in the design.  ...  An FIR filter is used to perform filtering and it can have different shapes in its transfer function, which is the Fourier transform of its impulse response.  ... 
doi:10.1109/vlsid.2011.58 dblp:conf/vlsid/KunaparajuNB11 fatcat:lyjvho7l7zct7fd36gfucaztzy

Performance Analysis of Timing-Speculative Processors

Omid Assare, Rajesh Gupta
2021 IEEE transactions on computers  
I am grateful for the freedom I had to explore and change direction and the opportunity to learn and practice independent thinking. It has been an honor to work under his supervision.  ...  Error signals of all Figure 2 . 2 7a and 2.7b show the microarchitecture design of counterflow pipelining and a timing diagram of the pipeline during the recovery of a timing error in the EX stage.  ...  Figure 2 . 2 6a and 2.6b show the microarchitecture design of clock gating and a timing diagram of the pipeline during the recovery of a timing error in the EX stage.  ... 
doi:10.1109/tc.2021.3051877 fatcat:nkkie5fnx5hybmnjaf52qux36y

Millions of little minions

Vimalkumar Jeyakumar, Mohammad Alizadeh, Yilong Geng, Changhoon Kim, David Mazières
2014 Proceedings of the 2014 ACM conference on SIGCOMM - SIGCOMM '14  
Our design leverages what each component does best: (a) switches forward and execute tiny packet programs (at most 5 instructions) in-band at line rate, and (b) end-hosts perform arbitrary (and easily  ...  Using a hardware prototype on a NetFPGA, we show our design is feasible at a reasonable cost.  ...  Navindra Yadav for helpful feedback and discussions that shaped this work.  ... 
doi:10.1145/2619239.2626292 dblp:conf/sigcomm/JeyakumarAGKM14 fatcat:evkwjn7fsvcxvodylrmejthrdq

Millions of little minions

Vimalkumar Jeyakumar, Mohammad Alizadeh, Yilong Geng, Changhoon Kim, David Mazières
2014 Computer communication review  
Our design leverages what each component does best: (a) switches forward and execute tiny packet programs (at most 5 instructions) in-band at line rate, and (b) end-hosts perform arbitrary (and easily  ...  Using a hardware prototype on a NetFPGA, we show our design is feasible at a reasonable cost.  ...  Navindra Yadav for helpful feedback and discussions that shaped this work.  ... 
doi:10.1145/2740070.2626292 fatcat:z46wkjbrxfbipgqb44uqush56q

Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

Holger Orup
1995 DAIMI Report Series  
This Ph.D. thesis treats the calculation of modular exponentials using very large operands.  ...  A very fast VLSI processor has been designed, constructed, and tested.  ...  Acknowledgements I am truly grateful for the inspiration, advice and support I have received from many people during my work on this thesis.  ... 
doi:10.7146/dpb.v24i499.7027 fatcat:7pa6kgr4yvcgrflmevv5c5y47q

Millions of Little Minions: Using Packets for Low Latency Network Programming and Visibility (Extended Version) [article]

Vimalkumar Jeyakumar, Mohammad Alizadeh, Yilong Geng, Changhoon Kim,, David Mazières
2014 arXiv   pre-print
And finally, we present an architecture in which they can be made secure.  ...  Our design leverages what each component does best: (a) switches forward and execute tiny packet programs (at most 5 instructions) at line rate, and (b) end-hosts perform arbitrary computation on network  ...  Navindra Yadav for helpful feedback and discussions that shaped this work.  ... 
arXiv:1405.7143v3 fatcat:3uccdh5cfrfthmqn4gqnjrafw4

Final Statements [chapter]

2009 FPGA-Based Implementation of Signal Processing Systems  
A number of other people have also acted to contribute in many other ways to either provide technical input or support. These  ...  The authors would like to thank Richard Walke and John Gray for motivating a lot of the work at Queen's University Belfast on FPGA.  ...  These extra cycles are reflected in the truncation term within the latency expression. The value of the term depends on the output data time shape and on which output bit the truncation is applied.  ... 
doi:10.1002/9780470713785.ch14 fatcat:b5uyg6k2qbhnncscazm2ickxki

An Overview of the BlueGene/L Supercomputer

N.R. Adiga, G. Almasi, G.S. Almasi, Y. Aridor, R. Barik, D. Beece, R. Bellofatto, G. Bhanot, R. Bickford, M. Blumrich, A.A. Bright, J. Brunheroto (+103 others)
2002 ACM/IEEE SC 2002 Conference (SC'02)  
The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures.  ...  Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions, including the San Diego Supercomputer Center and the California  ...  The torus network provides both adaptive and deterministic minimal-path routing, and is deadlock free.  ... 
doi:10.1109/sc.2002.10017 dblp:conf/sc/AdigaAA02 fatcat:b5nxrp7mubekdhfsvnlklreahy

A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography [article]

Xiaoxuan Lou, Tianwei Zhang, Jun Jiang, Yinqian Zhang
2021 arXiv   pre-print
Since these are hardware attacks targeting software, we summarize the vulnerable implementations in software, as well as flawed designs in hardware. (2) We identify common strategies to mitigate microarchitectural  ...  Side-channel attacks have become a severe threat to the confidentiality of computer applications and systems.  ...  Modern pipeline designs support Simultaneous Multithreading (SMT), where multiple threads can execute concurrently in the pipeline.  ... 
arXiv:2103.14244v1 fatcat:u35eyivqbngplfa4qrswfsqqti

FloatX

Goran Flegar, Florian Scheidegger, Vedran Novaković, Giovani Mariani, Andrés E. Tom´s, A. Cristiano I. Malossi, Enrique S. Quintana-Ortí
2019 ACM Transactions on Mathematical Software  
The paper discusses in detail the design principles, programming interface and datatype casting rules behind FloatX.  ...  We present FloatX (Float eXtended), a C++ framework to investigate the effect of leveraging customized floating-point formats in numerical applications.  ...  The common type is determined at compile time, using a combination of meta-programming techniques including: trait classes for built-in and FloatX-provided types, SFINAE (Substitution Failure Is Not An  ... 
doi:10.1145/3368086 fatcat:5iisoygvonf5hbra44kvjsxlqy

Design of large polyphase filters in the Quadratic Residue Number System

Gian Carlo Cardarilli, Alberto Nannarelli, Yann Oster, Massimo Petricca, Marco Re
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
Naïve subjects are able to control and navigate the robot via the designed interface with minimal practice and classifier calibration.  ...  design of a combined binary/decimal multi-operand adder intended for high performance applications.  ... 
doi:10.1109/acssc.2010.5757589 fatcat:ccxnu5owr5fyrcjcqukumerueq

Learning Capacity in Simulated Virtual Neurological Procedures

Mattia Samuel Mancosu, Silvester Czanner, Martin Punter
2020 Journal of WSCG  
This work was partially supported by a grant of Ministry of Research and Innovation, CNCS -UEFISCDI, project number PN-III-P4-ID-PCE-2016-0842, within PNCDI III.  ...  ACKNOWLEDGMENTS The authors acknowledge the support of the NSERC/Creaform Industrial Research Chair on 3-D Scanning for conducting the work presented in this paper.  ...  However, an attempt is made to maximally reduce the size of the shape description vector in order to minimize the storage space and to reduce the matching time.  ... 
doi:10.24132/csrn.2020.3001.13 fatcat:uytlm7nytrhmnk553ellfhl54a

Implementation of Fog computing for reliable E-health applications

Razvan Craciunescu, Albena Mihovska, Mihail Mihaylov, Sofoklis Kyriazakos, Ramjee Prasad, Simona Halunga
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
An important aspect is robust and resource efficient preamble design to minimize missed detection and false alarm probabilities of service requests.  ...  In this paper we compare one-stage and two-stage radio access protocol options tailored for sporadic transmissions of small data packets in uplink with respect to throughput and delay requirements.  ...  These MBE multipliers typically encode only one operand of the multiplier, and we observe this asymmetry results in different power characteristics as each input transitions to the next value in a pipelined  ... 
doi:10.1109/acssc.2015.7421170 dblp:conf/acssc/CraciunescuMMKP15 fatcat:qm6mki5z6bcvrfimkmqjyrxaxm

Ping-pong beam training for reciprocal channels with delay spread

Elisabeth de Carvalho, Jorgen Bach Andersen
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
We analyze the impact of compute and forward in minimizing the time to empty a wireless network. While a Linear Programing formulation is available, the minimization problem remains NP-hard.  ...  An important aspect is robust and resource efficient preamble design to minimize missed detection and false alarm probabilities of service requests.  ...  These MBE multipliers typically encode only one operand of the multiplier, and we observe this asymmetry results in different power characteristics as each input transitions to the next value in a pipelined  ... 
doi:10.1109/acssc.2015.7421451 dblp:conf/acssc/CarvalhoA15 fatcat:mqokuvnh3zg45licnfbgxyvxfu
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