A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
SiGe slips into main fabs
2004
III-Vs review
Preserved Fulltext
CMOS silicon's speed can be boosted by shrinking transistor dimension from 130nm to firstly 90nm then 65nm and 45nm, but only at great expense and difficulty, especially as the limits of CMOS scaling are ...
, from less than $0.5mn to $3bn, (almost half for cell phones.) ...
doi:10.1016/s0961-1290(04)00281-9
fatcat:eb6zz4rldnhmvgup2b5tzfguiy
Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications
2017
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital" transmitters to realize high-speed long-haul links at millimeter-wave frequencies ...
in 45nm SOI CMOS. ...
The eighth broadband progress report from the FCC has concluded that "broadband is not being reasonably and timely deployed to all Americans" particularly for data rates exceeding 3Mb/s [117, 118] . ...
doi:10.7916/d8xp74vt
fatcat:zxlenm2axrgsdjiout4iklm5i4
Memory leads the way to better computing
2015
Nature Nanotechnology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The goal of the study was to assay the state of the art, and not to either propose a potential system or prepare and propose a detailed roadmap for its development. ...
The report itself was drawn from the results of a series of meetings over the second half of 2007, and as such reflects a snapshot in time. ...
It plots simulated energy efficiency for the above logic test chip in 65nm, 45nm, and 32nm technologies, with variation in threshold voltage (V t ) of 0 and +/-50mV. ...
doi:10.1038/nnano.2015.29
pmid:25740127
fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m