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Fully Pipelined Soft Vector Processor as a CPU Accelerator

Yeyong Pang, Shaojun Wang, Yu Peng, Xiyuan Peng
2017 Chinese journal of electronics  
A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability.  ...  FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks.  ...  So this architecture features both microprocessor's flexibility as well as parallel accelerator's high performance. Microcoding implementations of three typical data-parallel algorithms are verified.  ... 
doi:10.1049/cje.2017.09.014 fatcat:haw5oowrfbd5dfglb4jqpyieve

MCGREP--A Predictable Architecture for Embedded Real-Time Systems

Jack Whitham, Neil Audsley
2006 2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)  
MCGREP is implemented upon reconfigurable logic (FPGA) -an increasingly important platform for the embedded RTS. Custom microcode configurations for new instructions are generated from C source.  ...  This paper proposes MCGREP, a novel CPU architecture that combines predictability, high instruction throughput and flexibility. MCGREP is entirely microprogrammed, with multiple execution units.  ...  Thus, there is a tradeoff between resource efficiency and flexibility. Architectures that use software on a general purpose CPU are moderately flexible, as the software can be changed.  ... 
doi:10.1109/rtss.2006.28 dblp:conf/rtss/WhithamA06 fatcat:s5pz3vqeefdpvpd5natc5c3pqu

Efficient hardware for multiway jumps and pre-fetches

K. Karplus, A. Nicolau
1985 ACM SIGMICRO Newsletter  
This is typically used for microcoded case statements such as opcode decoding. A more flexible approach was suggested by Fisher[Fisher80] .  ...  Hardwiring the tests for the microinstruction loses the flexibility required to handle the variety of combinations of tests that arise when compacting general-purpose code.  ... 
doi:10.1145/18906.18908 fatcat:hlmwe35s2jhczjs2k3vunxq5ci

Efficient hardware for multiway jumps and pre-fetches

K. Karplus, A. Nicolau
1985 Proceedings of the 18th annual workshop on Microprogramming - MICRO 18  
This is typically used for microcoded case statements such as opcode decoding. A more flexible approach was suggested by Fisher[Fisher80] .  ...  Hardwiring the tests for the microinstruction loses the flexibility required to handle the variety of combinations of tests that arise when compacting general-purpose code.  ... 
doi:10.1145/18927.18908 dblp:conf/micro/KarplusN85 fatcat:76h54dv4obfepcxezp4a3gbobi

Polymorphic architectures

Georgi Kuzmanov
2009 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing - CompSysTech '09  
Its operation is based on the co-processor architectural paradigm and employs the concept of the traditional microcode control.  ...  The base architecture presented is the Molen polymorphic processor -a synergism between a general purpose processor (GPP) and a reconfigurable accelerator.  ...  The described work would not be possible without the foundations he laid for it.  ... 
doi:10.1145/1731740.1731745 dblp:conf/compsystech/Kuzmanov09 fatcat:otowy7tktray3gpbubpa7ztqcu

On the Design and Misuse of Microcoded (Embedded) Processors - A Cautionary Note

Nils Albartus, Clemens Nasenberg, Florian Stolz, Marc Fyrbiak, Christof Paar, Russell Tessier
2021 USENIX Security Symposium  
Unfortunately, microcode update flexibility opens up new attack vectors through malicious microcode alterations.  ...  We introduce the design of a microcoded RISC-V processor architecture together with a microcode development and evaluation environment.  ...  input regarding microcoded RISC-V architectures.  ... 
dblp:conf/uss/AlbartusNSFPT21 fatcat:43b3ogfy5zdedoq2uy2jfmkju4

PISC: Polymorphic Instruction Set Computers [chapter]

Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu-Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
2006 Lecture Notes in Computer Science  
More specifically, we address a new framework for tools, supporting reconfigurability; new architectural and microarchitectural concepts; new programming paradigm allowing hardware and software to coexist  ...  Overall, the PISC paradigm allows designers to ride the Amdahl's curve easily by considering the specific features of the reconfigurable technology and the general purpose processors in the context of  ...  This new computing paradigm allows general purpose programming code and reconfigurable hardware descriptions to coexist within the same application program.  ... 
doi:10.1007/11802839_36 fatcat:avl2mngukngvda5wfuxaord2cy

The MOLEN polymorphic processor

S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E.M. Panainte
2004 IEEE transactions on computers  
To achieve the previously stated attributes, we present a new programming paradigm, a new instruction set architecture, a microcode-based microarchitecture, and a compiler methodology.  ...  In our proposal, for a given instruction set architecture, a onetime instruction set extension of eight instructions is sufficient to implement the reconfigurable functionality of the processor.  ...  ACKNOWLEDGMENTS This research is partially supported by PROGRESS, the embedded systems research program of the Dutch organization for Scientific Research NWO.  ... 
doi:10.1109/tc.2004.104 fatcat:ohon5wei7neohoi7e5l3gzzxtq

Progress in a novel architecture for high performance processing

Zhiwei Zhang, Meng Liu, Zijun Liu, Xueliang Du, Shaolin Xie, Hong Ma, Guangxin Ding, Weili Ren, Fabiao Zhou, Wenqin Sun, Huijuan Wang, Donglin Wang
2018 Japanese Journal of Applied Physics  
The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance.  ...  The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU).  ...  As shown in Fig. 3 , MaPU (the first generation of HPP) architecture is made up of three main components: microcode pipeline, multi-granularity parallel memory and scalar pipeline.  ... 
doi:10.7567/jjap.57.04fa03 fatcat:gzaau2ryf5a43ccyxub672k5ei

Architecture synthesis of high-performance application-specific processors

Mauricio Breternitz, John Paul Shen
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
The powerful microcode compilation techniques of Percolation Scheduling and Pipeline Scheduling extract and enhance the parallelism in the application object code to generate an optimized specification  ...  of the target processor.  ...  Parallelized microcode for the innermost loop is presented in Figure 6 below.  ... 
doi:10.1145/123186.123398 dblp:conf/dac/BreternitzS90 fatcat:h5lhg46wtzhijefjimgjwczz5i

Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings

Milad Bahadori, Kimmo Järvinen
2020 Zenodo  
We also show that the architecture can support different types of pairings via microcode updates and can be implemented on other reprogrammable devices with very minor modifications.  ...  In this paper, we present a compact and programmable yet high-performance architecture for programmable system-onchip platforms designed for efficient computation of different cryptographic pairings.  ...  The architecture is optimized for the resources of modern reprogrammable SoCs such as DSPs, BlockRAMs, and hard ARM cores. • The architecture supports microcode updates that can be used for supporting  ... 
doi:10.5281/zenodo.3991593 fatcat:oxwzaauwjjanfkibh6pjwnxtie

400 Gb/s Programmable Packet Parsing on a Single FPGA

Michael Attig, Gordon Brebner
2011 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems  
Compilation involves generating virtual processing architectures tailored to specific packet parsing requirements.  ...  Run-time programmability of these architectures allows dynamic updating of parsing algorithms during operation in the field.  ...  Figure 2 shows the internal micro-architecture template for the pipeline stages generated by the PP compiler.  ... 
doi:10.1109/ancs.2011.12 dblp:conf/ancs/AttigB11 fatcat:6uxiak34zfbahhrvtgcktfyyiy

On Horizontally Microprogrammed Microarchitecture Description Techniques

J.L. Gieser
1982 IEEE Transactions on Software Engineering  
In automatically generating microcode starting from a highlevel source language, a significant issue is the description of the target microengine architecture.  ...  Its objective is to identify the techniques that appear to have the most promise for use in interjecting the target microarchitecture characteristics into the high-level language-to-microcode compilation  ...  This information would then be used to prepare input that could be referenced by a generalized microcode generator to create microcode for that target magchine.  ... 
doi:10.1109/tse.1982.235739 fatcat:fs6oaisf7zgtrgqyli36i6pqaa

A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory

Youngkyu Park
2013 ETRI Journal  
To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed.  ...  Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory.  ...  By decoding the microcode sequence, test patterns based on the target test algorithm are generated using the BIST logic.  ... 
doi:10.4218/etrij.13.0112.0717 fatcat:sbuf2dr3j5eytixhxnpoosgp7u

Loading ρμ-Code: Design Considerations [chapter]

Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
2004 Lecture Notes in Computer Science  
This article investigates microcode generation, finalization and loading in MOLEN ρµ processors.  ...  In addition, general solutions for these issues are presented and implementation for Xilinx Virtex-II Pro platform FPGA is introduced.  ...  in the targeted memory architecture.  ... 
doi:10.1007/978-3-540-27776-7_2 fatcat:kefstn4ypbf5tajrntknmttuuq
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