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Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System

Henry Wong, Vaughn Betz, Jonathan Rose
2016 ACM Transactions on Reconfigurable Technology and Systems  
In this article, we describe and explore microarchitectural and circuit-level tradeoffs in the design of such a memory system.  ...  Superscalar out-of-order processors promise large performance gains, and the memory subsystem is a key part of such a processor that must help supply increased performance.  ...  high frequency (200 MHz), which is faster than most in-order soft processors and within 17% of the 240 MHz Nios II/f.  ... 
doi:10.1145/2974022 fatcat:szfkgp7uybb57jcvwa3dhvcet4

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Henry Wong, Vaughn Betz, Jonathan Rose
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates, then uses these results to show how soft processor  ...  Applying these results, we find out-of-order soft processors should use physical register file organizations to minimize CAM size. Henry Wong is pursuing the Ph.D. degree from the  ...  Out-of-Order Microarchitecture Superscalar out-of-order processors are more complex than single-issue in-order processors.  ... 
doi:10.1109/tvlsi.2013.2284281 fatcat:klebm46zxzh45nsinntrpcug6q

An architecture for exploiting coarse-grain parallelism on FPGAs

Davor Capalija, Tarek S. Abdelrahman
2009 2009 International Conference on Field-Programmable Technology  
The central component of the MLCA is its Control Processor (CP), which is analogous to an out-of-order scheduling unit of a superscalar processor.  ...  In this paper, we explore the FPGA implementation of the CP and demonstrate the scalability of the MLCA for multimedia applications. We design, test and evaluate an 8-PU MLCA system.  ...  Our system consists of 8 PUs with caches and is organized as a shared memory multiprocessor.  ... 
doi:10.1109/fpt.2009.5377658 fatcat:eqgmfxouazdajiaumk7fezp62m

A survey of multicore processors

Geoffrey Blake, Ronald Dreslinski, Trevor Mudge
2009 IEEE Signal Processing Magazine  
The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals. [ A review of their common attributes ]  ...  G eneral-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability  ...  integrated circuits (ASICs) as part of a "system on chip."  ... 
doi:10.1109/msp.2009.934110 fatcat:bz43svicrrgt5ez37hztkqalwa

A Multithreaded Soft Processor for SoPC Area Reduction

Blair Fort, Davor Capalija, Zvonko Vranesic, Stephen Brown
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-a-Programmable-Chip (SoPC) designers to use soft processors for controlling systems with large numbers  ...  This paper presents a multithreaded (MT) soft processor for area reduction in SoPC implementations.  ...  Acknowledgments This work was supported in part by NSERC, and the Edward S. Rogers Sr. Scholarship. We would like to thank Franjo Plavec for his advice and direction.  ... 
doi:10.1109/fccm.2006.10 dblp:conf/fccm/FortCVB06 fatcat:ucepgze7qvfwfkk5c2a2dmv7su

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Mile Stojcev, Teufik Tokic, Ivan Milentijevic
2004 Facta universitatis - series Electronics and Energetics  
The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide.  ...  The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution, out-of-order  ...  It is a job of the microarchitecture, the logic, and the circuits to carry out this instruction stream in the "best" way [20] .  ... 
doi:10.2298/fuee0403285s fatcat:gaxelp2aebbnvinhxssaydxhvy

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd Austin, David Blaauw
2005 SIGARCH Computer Architecture News  
Sensor network processors and their applications are a growing area of focus in computer system research and design.  ...  We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures.  ...  We would like to thank Valeria Bertacco for her input to this paper. This work is supported by grants from NSF and the Gigascale Systems Research Center.  ... 
doi:10.1145/1080695.1069987 fatcat:tsgiwsprebbmlbtcm34b4uhnzi

Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs

Jose Luis Nunez-Yanez
2015 IEEE transactions on computers  
As a result, voltage scaling is often combined with frequency scaling in order to compensate for the variation of circuit delay.  ...  Test system A test system based around the Cortex M0 processor from ARM has been built to test the capabilities and limitations of the system.  ... 
doi:10.1109/tc.2014.2365963 fatcat:fpbjprqw3rgb3nkcj53zs37cy4

Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors

Changyun Zhu, Zhenyu Gu, Li Shang, Robert P. Dick, Robert G. Knobel
2007 Proceedings - Design Automation Conference  
Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling.  ...  This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs.  ...  This synthesis flow permitted the system-level evaluation of all microarchitectural components in Table III except for multi-gate exclusive-or and fast carry-out logic.  ... 
doi:10.1109/dac.2007.375178 fatcat:254hurvwzbcjbp7jh2g4vzpbwa

Understanding soft errors in uncore components

Hyungmin Cho, Chen-Yong Cher, Thomas Shepherd, Subhasish Mitra
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
However, little has been published about soft errors in uncore components, such as memory subsystem and I/O controllers, of a System-on-a-Chip (SoC).  ...  The effects of soft errors in processor cores have been widely studied.  ...  The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.  ... 
doi:10.1145/2744769.2744923 dblp:conf/dac/ChoCSM15 fatcat:dg2c6zn2tfg75jjlv2tsxdf2zq

Custom FPGA-based soft-processors for sparse graph acceleration

Nachiket Kapre
2015 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
ZC706 board (100 processor design) across a range of matrix datasets.  ...  We outperform a Microblaze (100 MHz on Zedboard) and an NIOS-II/f (100 MHz on DE2-115) by ≈6× (single processor design) as well as the ARMv7 dual-core CPU on the Zynq SoCs by as much as 10× on the Xilinx  ...  We target and achieve an initiation interval of 1 and a system frequency of 200 MHz (Zedboard) and 250 MHz (ZC706) allowing fully-pipelined operation.  ... 
doi:10.1109/asap.2015.7245698 dblp:conf/asap/Kapre15 fatcat:mqos2rxf4zdkxcsq2hf6q3xji4

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

D. Brooks, R.P. Dick, R. Joseph, Li Shang
2007 IEEE Micro  
Engineering Research Council of Canada under Discovery Grant 388694-01.  ...  Acknowledgments This work was supported in part by the US National Science Foundation under awards CCF-0048313 and CNS-0347941, in part by Intel, in part by IBM, and in part by the Natural Sciences and  ...  Mid-frequency noise in the range of 50 to 200 MHz and high-frequency noise near the processor clock rate have achieved the most attention in the literature.  ... 
doi:10.1109/mm.2007.58 fatcat:gebuecbksrgthitqhcvrd2mp2e

Robust low power computing in the nanoscale era

Todd Austin
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
from cosmic radiation and alpha particles radiation Appears to be a reliability threat for future technology processors When a particle strikes a circuit element a small amount of charge is deposited  ...  Error Rate Trends, ITRS03 Soft Error Rate Trends, ITRS03 Impact of Soft Errors in Processors Impact of Soft Errors in Processors [Iyer] [Iyer] How do soft errors in processors propagate and impact  ... 
doi:10.1145/1150343.1150352 dblp:conf/sbcci/Austin06 fatcat:7cdhgdke4raevpc7m2plec6fjq

Towards an ultra-low-power architecture using single-electron tunneling transistors

Changyun Zhu, Zhenyu (Peter) Gut, Li Shang, Robert P. Dick, Robert G. Knobel
2007 Proceedings - Design Automation Conference  
Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling.  ...  This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs.  ...  This synthesis flow permitted the system-level evaluation of all microarchitectural components in Table III except for multi-gate exclusive-or and fast carry-out logic.  ... 
doi:10.1145/1278480.1278560 dblp:conf/dac/ZhuGSDK07 fatcat:nft5ckx5ovfbpkfjfur2ydv4ji

Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone
2021 Computer Science Review  
The focus is on soft errors, which dominate the failure rate of processors in space.  ...  For these case studies, several types of redundancy described in literature for space processors will be evaluated in terms of their cost-effectiveness and expected final in-orbit behavior.  ...  Acknowledgments This work was supported by the European Space Agency under the NPI Program, Cobham Gaisler AB, and Delft University of Technology.  ... 
doi:10.1016/j.cosrev.2020.100349 fatcat:la3jkrklerf4fff2iqu5fkhhpy
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