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Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

R. Balasubramonian, N. Muralimanohar, K. Ramani, V. Venkatachalapathy
11th International Symposium on High-Performance Computer Architecture  
In such architectures, inter-partition communication over global wires has a significant impact on overall processor performance and power consumption.  ...  Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power.  ...  We therefore make a case for microarchitectural wire management in future communication-bound processors.  ... 
doi:10.1109/hpca.2005.21 dblp:conf/hpca/BalasubramonianMRV05 fatcat:i2bbg74xt5czlkoj7646kyzkry

Instruction Level Distributed Processing [chapter]

J. E. Smith
2000 Lecture Notes in Computer Science  
The complexity is not just in critical path lengths and transistor counts: There is high intellectual complexity in the increasingly intricate schemes for squeezing performance out of second-and third-order  ...  Wire delays Both short (local) and long (global) wires cause problems for microprocessor designers.  ...  Acknowledgments I thank the National Science Foundation (grant CCR-9900610), IBM, Sun Microsystems, and Intel for supporting this work.  ... 
doi:10.1007/3-540-44467-x_22 fatcat:bkqc56v7rzbwvl5ad2p2xxl43a

Instruction-level distributed processing

J.E. Smith
2001 Computer  
The complexity is not just in critical path lengths and transistor counts: There is high intellectual complexity in the increasingly intricate schemes for squeezing performance out of second-and third-order  ...  Wire delays Both short (local) and long (global) wires cause problems for microprocessor designers.  ...  Acknowledgments I thank the National Science Foundation (grant CCR-9900610), IBM, Sun Microsystems, and Intel for supporting this work.  ... 
doi:10.1109/2.917541 fatcat:eznn2kponjai3pnbf4p2komg34

Design space exploration for 3D architectures

Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein
2006 ACM Journal on Emerging Technologies in Computing Systems  
As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors.  ...  As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures.  ...  Nick Samra from Intel Corporation worked on the microarchitecture of the microprocessor described in Section 5.  ... 
doi:10.1145/1148015.1148016 fatcat:752rniivarf4hn5lmnmrtp2acy

Low-cost router microarchitecture for on-chip networks

John Kim
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
The challenge for on-chip network is to reduce the cost including power consumption and area while providing high performance such as low latency and high bandwidth.  ...  We reduce the cost of on-chip networks by partitioning the crossbar, prioritizing packets in flight to simplify arbitration, and reducing the amount of buffers.  ...  Acknowledgments We would like to thank the anonymous reviewers for their comments. This work was supported in part by the KAIST-Microsoft Research Collaboration Center (KMCC) at KAIST, Korea.  ... 
doi:10.1145/1669112.1669145 dblp:conf/micro/Kim09 fatcat:z7kdn7xwo5hs5gphversqnsisq

Processor Design in 3D Die-Stacking Technologies

Gabriel H. Loh, Yuan Xie, Bryan Black
2007 IEEE Micro  
For longer wires, the wire-length reduction will bring an improvement in both latency and power.  ...  First, eliminating critical wires can result in simultaneous latency and power reductions; contrast this with the typical case where a power reduction usually results in a performance drop as well.  ... 
doi:10.1109/mm.2007.59 fatcat:lpufanhsefg5hc5nwcv5tt3pfi

Billion-transistor architectures: there and back again

D. Burger, J.R Goodman
2004 Computer  
The second set described a number of visions for designs that could and would scale up to billion-transistor architectures (BTAs).  ...  We solicited and selected two sets of papers. The first set enumerated important emerging trends that were potential drivers of architectural change in technology, applications, and interfaces.  ...  The increasing wire delays that Matzke described are forcing greater partitioning of hardware, which could in turn force more partitioning of software.  ... 
doi:10.1109/mc.2004.1273999 fatcat:g3pgpbucqfbnbjdjdvxrygjtui

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents the first multiobjective microarchitectural floorplanning algorithm for high-performance processors implemented in two-dimensional (2-D) and three-dimensional (3-D) ICs.  ...  This paper provides comprehensive experimental results on making tradeoffs among performance, thermal, area, and wirelength for both 2-D and 3-D ICs.  ...  A. 3-D Extension of Architectural Simulation In order to support the performance, power, and thermal simulation for 3-D microarchitecture floorplanning, we extend the simulation engines discussed in Section  ... 
doi:10.1109/tcad.2006.883925 fatcat:ss7qynacpzawbkh4wy5asaz6ey

Early chip planning cockpit

Jeonghee Shin, J A Darringer, Guojie Luo, A J Weger, C L Johnson
2011 2011 Design, Automation & Test in Europe  
In this paper, we introduce an Early Chip Planner which allows designers to rapidly analyze microarchitecture, physical and package design trade-offs for 2D and 3D VLSI chips and generates an attributed  ...  The design of high-performance servers has always been a challenging art.  ...  ACKNOWLEDGMENT We would like to thank our colleagues at IBM who have been working with us and provided invaluable insights; special thanks to Pradip Bose, Alper Buyuktosunoglu and Eren Kursun.  ... 
doi:10.1109/date.2011.5763292 dblp:conf/date/ShinDLWJ11 fatcat:6hxwsjzlubczvbquicgfngfdce

Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs

Antonio Flores, Juan L. Aragon, Manuel E. Acacio
2010 IEEE transactions on computers  
Moreover, wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.  ...  In this work, we show how messages can be efficiently managed, from the point of view of both performance and energy, in tiled CMPs using a heterogeneous interconnect.  ...  ACKNOWLEDGMENTS This work has been jointly supported by the Spanish MEC and European Commission FEDER funds under grants "Consolider Ingenio-2010 CSD2006-00046" and "TIN2006-15516-C4-03," and also by the  ... 
doi:10.1109/tc.2009.129 fatcat:fsdidixrz5cgdk6nbdhh47gopy

Microarchitectural Floorplanning Under Performance and Thermal Tradeoff

M. Healy, M. Vittes, M. Ekpanyapong, C. Ballapuram, Sung Kyu Lim, H.-H.S. Lee, G.H. Loh
2006 Proceedings of the Design Automation & Test in Europe Conference  
Our floorplanner takes a microarchitectural netlist and determines the placement of the functional modules while simultaneously optimizing for performance and thermal reliability.  ...  In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design phase.  ...  Microarchitectural Model In order to model performance more faithfully for deep submicron processors, we isolate and model each wire as a separate resource which consumes power and has a delay in proportion  ... 
doi:10.1109/date.2006.244102 dblp:conf/date/HealyVEBLLL06 fatcat:ukiqg6rsunetdexqqhpykykwve

A modular 3d processor for flexible product design and technology migration

Gabriel H. Loh
2008 Proceedings of the 2008 conference on Computing frontiers - CF '08  
We present a modular processor architecture where 3D can be used to enhance performance within a single unified design and also provides for a more gradual migration path toward fully 3D-integrated designs  ...  markets and a separate 2D microarchitecture must be designed for the lower-cost markets thereby incurring significant additional design effort and engineering cost.  ...  Acknowledgments This project was funded by NSF grant CCF-0643500; support was also provided by the Focus Center for Circuit & System Solutions (C2S2), one of five research centers funded under the Focus  ... 
doi:10.1145/1366230.1366261 dblp:conf/cf/Loh08 fatcat:tzgrm6bygndzjl2omqracnulea

Composable Lightweight Processors

Changkyu Kim, Simha Sethumadhavan, M.S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
Simulation results show that CLPs achieve an average performance boost of 42%, an average area-efficiency of 3.4x, and an average power-efficiency of 2x over a fixed architecture on a spectrum of single-threaded  ...  This paper evaluates a flexible architectural approach, called Composable Lightweight Processors (or CLPs), that allows simple, low-power cores to be aggregated together dynamically, forming larger, more  ...  Acknowledgments We thank Ramdass Nagarajan, Haiming Liu, Mark Gebhart, Bert Maher, Katherine Coons, Jeff Diamond and Behnam Robatmilli for their contribution to the paper.  ... 
doi:10.1109/micro.2007.4408270 fatcat:m2zm2hxwczfc5gfihtqhmqe63a

Composable Lightweight Processors

Changkyu Kim, Simha Sethumadhavan, M.S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
Simulation results show that CLPs achieve an average performance boost of 42%, an average area-efficiency of 3.4x, and an average power-efficiency of 2x over a fixed architecture on a spectrum of single-threaded  ...  This paper evaluates a flexible architectural approach, called Composable Lightweight Processors (or CLPs), that allows simple, low-power cores to be aggregated together dynamically, forming larger, more  ...  Acknowledgments We thank Ramdass Nagarajan, Haiming Liu, Mark Gebhart, Bert Maher, Katherine Coons, Jeff Diamond and Behnam Robatmilli for their contribution to the paper.  ... 
doi:10.1109/micro.2007.41 dblp:conf/micro/KimSGRGBK07 fatcat:rlbsu4nftjbchnxvxbqhs4gzsu

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert McDonald, Rajagopalan Desikan, Saurabh Drolia, M.S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan (+5 others)
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks.  ...  This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution.  ...  Acknowledgments We thank our design partners at IBM Microelectronics, and Synopsys for their generous university program.  ... 
doi:10.1109/micro.2006.19 dblp:conf/micro/SankaralingamNMDDGGGHKLRSSSKB06 fatcat:jiw42btzfbaujpk4efkrrhxhxu
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