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Methodology to derive resource aware context adaptable architectures for FPGAs

H. Samala, A. Dasu
2010 IET Computers & Digital Techniques  
In this paper, we present scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures.  ...  The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging  ...  CONCLUSION This paper presents a methodology to derive context adaptable architectures for FPGA that can support multiple DFGs contained in the CDFG of an application.  ... 
doi:10.1049/iet-cdt.2009.0047 fatcat:vjdb3jq6gndjfilwcpmyakoloy

From Reconfigurable Architectures to Self-Adaptive Autonomic Systems

Marco D. Santambrogio
2009 2009 International Conference on Computational Science and Engineering  
In order to overcome the limits deriving by the increasing complexity and the associated workload to maintain such complex infrastructure, one possibility is to adopt self-adaptive and autonomic computing  ...  A self-adaptive and autonomic computing system is a system able to configure, heal, optimize and protect itself without the need for human intervention.  ...  The current methodologies for Xilinx FPGAs [20] [21] , as an example, comprise a long series of steps that the developer has to undertake in order to convert the product of conventional CAD tools into  ... 
doi:10.1109/cse.2009.490 dblp:conf/cse/Santambrogio09 fatcat:4hzazfoovvfsrbypjtvygqbndq

Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)

Florian Dittmann, Franz J. Rammig, Martin Streubühr, Christian Haubelt, Andreas Schallenberg, Wolfgang Nebel
2007 it - Information Technology  
This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level  ...  They serve as run-time re-usable devices for performance critical data-oriented processes. However, the use of reconfigurable devices within large systems greatly increases the design complexity.  ...  In order to finally derive the best size for the configurations, we rely on the iterative behavior of our overall design methodology.  ... 
doi:10.1524/itit.2007.49.3.149 fatcat:gaabsiltkzhq3h54wcou2qw6he

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation.  ...  This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts.  ...  The adaptation of the algorithm considers that pre-located areas for loading of the contexts in the architecture are used. A power estimation tool for FPGA technology was developed.  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi

Design Methods for DSP Systems

Markus Rupp, Bernhard Wess, Shuvra S Bhattacharyya
2006 EURASIP Journal on Advances in Signal Processing  
In "3D-SoftChip: a novel architecture for next-generation adaptive computing systems," C.  ...  This special issue intends to present recent solutions to such gaps addressing algorithmic design methods, algorithms for floating-to-fixed-point conversion, automatic DSP coding strategies, architectural  ...  In "3D-SoftChip: a novel architecture for next-generation adaptive computing systems," C.  ... 
doi:10.1155/asp/2006/47817 fatcat:kzqolkoudjbh7eunsspbeatubq

A Real-Time Wideband Subband LMS Algorithm for Full-Duplex Communications

Kevin S. Lorenz, Joel Goodman, Michelle McBeth, Matthew B. McKeon, David J. Parrett
2022 IEEE Access  
INDEX TERMS Adaptive filters, least mean square methods, radio transceivers, radio communication.  ...  Digital signal processing to mitigate self-interference is one way to realize this full-duplex capability.  ...  A naive implementation of the adopted SAF architecture is shown in the block diagram in Fig. 2 , and while the methodology is correct, this architecture cannot operate at a sample rate of 2 Gsps due to  ... 
doi:10.1109/access.2022.3161548 fatcat:upixtqmmd5awpdg3cqokz56cgy

CAOS: CAD as an Adaptive Open-Platform Service for High Performance Reconfigurable Systems [chapter]

Marco Rabozzi
2019 SpringerBriefs in Applied Sciences and Technology  
In this chapter, we present CAD as an Adaptive Open-platform Service (CAOS), a platform to guide the application developer in the implementation of efficient hardware-software solutions for high performance  ...  Finally, CAOS is designed to facilitate the integration of external contributions and to foster research on Computer Aided Design (CAD) tools for accelerating software applications on FPGA-based systems  ...  an Adaptive Open-Platform Service for High Performance … CAOS: CAD as an Adaptive Open-Platform Service for High Performance … CAOS: CAD as an Adaptive Open-Platform Service for High Performance  ... 
doi:10.1007/978-3-030-32094-2_8 fatcat:zpang4mxhbarnacnihbujgjsya

FPGA-based smart camera mote for pervasive wireless network

Cedric Bourrasset, Jocelyn Serot, Francois Berry
2013 2013 Seventh International Conference on Distributed Smart Cameras (ICDSC)  
The classical programmability issue, a significant obstacle when dealing with FPGAs, is addressed by resorting to a domain specific high-level programming language (CAPH) for describing operations to be  ...  In this context, FPGA-based platforms, supporting massive, fine grain data parallelism, offer large opportunities.  ...  But, if FPGAs provide a suited hardware architecture to meet the constraints of high resolution real-time computation, they raise programmability issues, especially in the context of collaborative programming  ... 
doi:10.1109/icdsc.2013.6778226 dblp:conf/icdsc/BourrassetSB13 fatcat:ts5armn3ujdpvhmoy7i3bpe2tq

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform [chapter]

K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris, S. Nikolaidis
2004 Lecture Notes in Computer Science  
An AMDREL platform based reconfigurable SoC for a multi-mode wireless networking system is currently under development.  ...  In the context of the IST-AMDREL project, a mixed granularity reconfigurable SoC platform targeting wireless communication systems has been developed.  ...  Disclaimer The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose.  ... 
doi:10.1007/978-3-540-30205-6_63 fatcat:qjqoavk3erepfe22j7xvkkbr4q

Object-oriented domain specific compilers for programming FPGAs

O. Mencer, M. Platzner, M. Morf, M.J. Flynn
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper presents a methodology to combine true object-oriented design of the compiler/CAD tool with an object-oriented hardware design methodology in C++.  ...  Simplifying the programming models is paramount to the success of reconfigurable computing with field programmable gate arrays (FPGAs).  ...  ACKNOWLEDGMENT The authors would like to acknowledge the contributions of many students, current and past, to the JHDL system.  ... 
doi:10.1109/92.920835 fatcat:qm53w6pj6fa3fjxnskuqjq6xta

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

Marco D. Santambrogio, Donatella Sciuto
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
This paper presents emerging methodologies to design reconfigurable applications, providing, as an example the workflow defined at the Politecnico di Milano.  ...  Therefore, reconfigurable devices, such as FPGAs, introduce yet another degree of freedom in the design workflow: the designer can have the system autonomously modify the functionality carried out by the  ...  Classes implementing architectures have to be derived from a set of common interfaces provided in the framework.  ... 
doi:10.1109/ipdps.2008.4536542 dblp:conf/ipps/SantambrogioS08 fatcat:4sdexr5kozh6hgnguisr347voa

FPGA Design Methodology for Industrial Control Systems—A Review

E. Monmasson, M.N. Cirstea
2007 IEEE transactions on industrial electronics (1982. Print)  
These are: algorithm refinement, modularity and systematic search for the best compromise between the control performance and the architectural constraints.  ...  Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGAimplementation when using the proposed system modeling and design methodology.  ...  Acknowledgements are due to Dr. J. G. Khor, Mr. L. Charaâbi and Mr. W. Naouar for their research on some of the case studies presented.  ... 
doi:10.1109/tie.2007.898281 fatcat:l3f72ougkbbzzc4vo7sgogw2ku

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen
2010 Journal of systems architecture  
For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design.  ...  To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and  ...  As shown in Figure 7 , the wrapper architectures consist of a context buffer to store context data, a data path for data transfer, a swap controller to manage the swap-out and swap-in activities, and  ... 
doi:10.1016/j.sysarc.2010.07.007 fatcat:6lq7ebanfzd4vdhgprsy7p4uxe

Implementing High-Order FIR Filters in FPGAs [article]

Philipp Födisch, Artsiom Bryksa, Bert Lange, Wolfgang Enghardt, Peter Kaever
2016 arXiv   pre-print
Although this seems to be an easily implementable task, the synthesizing tools require an adaptation of the straightforward digital filter implementation for an optimal mapping.  ...  hardware architecture.  ...  Thus, the derived iterative mathematical functions for the systolic structure support the mapping of a digital filter to various architectures with different constraints.  ... 
arXiv:1610.03360v2 fatcat:qsggjkpcrbhclogbgyvjkncola

A run-time reconfigurable fuzzy PID controller based on modern FPGA devices

George Economakos, Christoforos Economakos
2007 2007 Mediterranean Conference on Control & Automation  
Modern FPGA architectures offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the  ...  Recent advances in device densities and the requirement for short time-to-market has made FPGA devices very popular for the implementation of general purpose electronic devices.  ...  FPGA Architecture for RTR FPGAs are the evolution of PLAs and PLDs.  ... 
doi:10.1109/med.2007.4433812 fatcat:n6qorwtcejgzpohdfwaia2xuhu
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