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Methodology for validating Nest Memory Management Unit

Nandhini Rajaiah, Jayakumar Sankarannair, Larry Leitner
2019 EAI Endorsed Transactions on Cloud Systems  
One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memory management unit for all I/O devices.  ...  Core MMU translation is used as the reference model to validate nest MMU.  ...  ., for his valuable feedback and support in completing this paper.  ... 
doi:10.4108/eai.15-3-2019.162139 fatcat:wnfxgv3bgnakri3pqcuz2pbcoa

PROMPT

Michel Barreteau, Juliette Mattioli, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Philippe Bonnot, Philippe Kajfasz
2000 Proceedings of the international conference on Compilers, architectures, and synthesis for embedded systems - CASES '00  
PLC2 automatically manages global constraints (e.g. latency) thanks to a constraints solver. SynDEx and EPHORAT are designed for validation, not for simulation.  ...  It is currently validated through a prototype environment which is based on the co-operation between two complementary methodologies.  ... 
doi:10.1145/354880.354887 dblp:conf/cases/BarreteauMGLSBK00 fatcat:oujnkk2tercbbnxupqclbtkofi

Architectural support for secure virtualization under a vulnerable hypervisor

Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
The hypervisor can still flexibly allocate physical memory pages to virtual machines for efficient resource management.  ...  The proposed mechanism extends the current hardware support for memory virtualization with a small extra hardware cost.  ...  H-SVM protects the memory of guest VMs from DMA, by extending IOMMU (I/O memory management unit), which is supported by both Intel VT-d and AMD-V [1, 18] .  ... 
doi:10.1145/2155620.2155652 dblp:conf/micro/JinACH11 fatcat:rtf76q5o7bdl5awcisryvdzaqa

The MOSART Mapping Optimization for Multi-Core ARchiTectures [chapter]

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani (+9 others)
2011 Lecture Notes in Electrical Engineering  
MOSART achieves this by: (i) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure;  ...  MOSART project addresses two main challenges of prevailing architectures: (i) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption  ...  memory hierarchy and provide runtime support for memory management and scheduling.  ... 
doi:10.1007/978-94-007-1488-5_11 fatcat:64p6g2afbbdrjjv5doxla5lmti

PICO: automatically designing custom computers

V. Kathail, S. Aditya, R. Schreiber, B. Ramakrishna Rau, D.C. Cronquist, M. Sivaraman
2002 Computer  
We thank Henk Corporaal for providing the code for the attractive GUI to his MOVE infrastructure, from which we Framework-based automation offers a powerful methodology for automating the design of complex  ...  processors and computer systems. developed PICO's GUI, and Wen-mei Hwu and his IMPACT group for providing Elcor's machineindependent front end.  ...  NPA DESIGN PICO-NPA accepts a loop nest in C, along with a range of performance requirements and available external memory bandwidth, and produces a Pareto set of NPAs customized for the given loop nest  ... 
doi:10.1109/mc.2002.1033026 fatcat:nqa5tazc5zfixew3lwznahgmne

Hierarchical multithreading: programming model and system software

G.R. Gao, T. Sterling, R. Stevens, M. Hereld, Weirong Zhu
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing.  ...  A methodology of incorporating domainspecific knowledge in program optimization will be studied.  ...  We would also like to acknowledge other members at the CAPSL group, who provide a stimulus environment for scientific discussions and collaborations, in particular Ziang Hu, Juan del Cuvillo, and Ge Gan  ... 
doi:10.1109/ipdps.2006.1639574 dblp:conf/ipps/GaoSSHZ06 fatcat:lkcf3jbp7jcr3mikequlczalhu

Advanced unit testing

Cyrille Artho, Armin Biere
2006 Proceedings of the 2006 international workshop on Automation of software test - AST '06  
By using a custom testing environment, functionality was extended beyond what is commonly available by unit test frameworks. Low-overhead memory leak detection was implemented through wrapping.  ...  Automated support for log files made it possible to track the internal state of objects, which is often much more expedient than writing test code.  ...  Memory Management For a better control of memory management, the standard memory allocation functions have been replaced.  ... 
doi:10.1145/1138929.1138947 dblp:conf/icse/ArthoB06 fatcat:2cq7c25canehxolfgmkzkcjyau

Localizing Tortoise Nests by Neural Networks

Roberto Barbuti, Stefano Chessa, Alessio Micheli, Rita Pucci, Gennady Cymbalyuk
2016 PLoS ONE  
The goal of this research is to recognize the nest digging activity of tortoises using a device mounted atop the tortoise carapace.  ...  Accelerometer data was collected from devices attached to the carapace of a number of tortoises during their two-month nesting period.  ...  in conservation management.  ... 
doi:10.1371/journal.pone.0151168 pmid:26985660 pmcid:PMC4795789 fatcat:wqbe5fef5zazrgi3fc4wbdgubu

Automatic performance model synthesis from hardware verification models

Robert H. Bell, Matyas Sustik, David W. Cummings, Jonathan R. Jackson
2011 Proceeding of the second joint WOSP/SIPEW international conference on Performance engineering - ICPE '11  
Performance models are typically written by hand for a new model or assembled piece-meal from the prior simulation code of an old model.  ...  In either case, many man-months of work may be required to write the new model and validate design details against a prior or current design.  ...  Units or specialized functions may be targeted, or nest or even unit performance models synthesized.  ... 
doi:10.1145/1958746.1958816 dblp:conf/wosp/BellSCJ11 fatcat:fyztn3fomjbfdf2sdg7xajvgyq

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani (+9 others)
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; 2  ...  ; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory.  ...  memory hierarchy and provide runtime support for memory management and scheduling.  ... 
doi:10.1109/isvlsi.2010.71 dblp:conf/isvlsi/CandaeleASAXBBSLCCHJVKTIKWVM10 fatcat:43mxty533vcnnp25k5vjmrpey4

Novel Methodologies for Predictable CPU-To-GPU Command Offloading

Roberto Cavicchioli, Nicola Capodieci, Marco Solieri, Marko Bertogna, Michael Wagner
2019 Euromicro Conference on Real-Time Systems  
analysis for the considered platforms.  ...  characterization of real-time tasks on high-performance heterogeneous embedded platforms, where a host system offloads parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing Units  ...  The captured traces for memory operations are identical in all the CUDA methodologies and do not increase with l, with Vulkan presenting 25% less memory management operations compared to CUDA.  ... 
doi:10.4230/lipics.ecrts.2019.22 dblp:conf/ecrts/CavicchioliCSB19 fatcat:syzck5enj5c5rkztwgny2xrv3a

Open nesting in software transactional memory

Yang Ni, Vijay S. Menon, Ali-Reza Adl-Tabatabai, Antony L. Hosking, Richard L. Hudson, J. Eliot B. Moss, Bratin Saha, Tatiana Shpeisman
2007 Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '07  
Here we present an implementation of open nested transactions in a Java-based software transactional memory (STM) system.  ...  Open nested transactions enable expert programmers to differentiate between physical conflicts, at the level of memory, and logical conflicts that actually violate application semantics.  ...  for long-running software transactions on a single thread by reducing the memory requirements of STM validation.  ... 
doi:10.1145/1229428.1229442 dblp:conf/ppopp/NiMAHHMSS07 fatcat:4svs556vubf6hcuhzqazbczdoq

On-chip memory space partitioning for chip multiprocessors using polyhedral algebra

O. Ozturk, M.J. Irwin, M. Kandemir
2010 IET Computers & Digital Techniques  
The second approach proposed consider dynamic configuration of software-managed on-chip memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns.  ...  patterns can change from one point in execution to another for the same application.  ...  memory design methodology that uses the same design for the entire execution of the application.  ... 
doi:10.1049/iet-cdt.2009.0089 fatcat:n4apvjbzsbd4hfex4x7cjer72e

An energy saving strategy based on adaptive loop parallelization

I. Kadayif, M. Kandemir, M. Karakoy
2002 Proceedings - Design Automation Conference  
nested loop in a multi-processor on-a-chip (MPoC) are shut down (i.e., placed into a power-down or sleep state).  ...  We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops.  ...  All functional unit energy models are for 0.35 micron technology and have been validated to be accurate (within 10%) [14] .  ... 
doi:10.1145/513918.513968 dblp:conf/dac/KadayifKK02 fatcat:u2iaesknijfyjettwkehs5b6wi

An energy saving strategy based on adaptive loop parallelization

I. Kadayif, M. Kandemir, M. Karakoy
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
nested loop in a multi-processor on-a-chip (MPoC) are shut down (i.e., placed into a power-down or sleep state).  ...  We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops.  ...  All functional unit energy models are for 0.35 micron technology and have been validated to be accurate (within 10%) [14] .  ... 
doi:10.1109/dac.2002.1012619 fatcat:xtcejmr4kbannlzy7k6z2s7kpq
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