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Memory-centric system interconnect design with hybrid memory cubes

Ankit Sethia, Ganesh Dasika, Mehrzad Samadi, Scott Mahlke
2013 Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques  
This translates to a 52% increase in performance per watt over systems with high multi-threading and 33% over existing GPU prefetching techniques.  ...  However, such designs do not translate well to mobile envi ronments where power constraints often limit the amount of hardware.  ...  Figure 4 compares the design of a traditional SM with an APOGEE SM. APOGEE interacts with the memory system and looks at the memory access pattern between the threads of a warp.  ... 
doi:10.1109/pact.2013.6618805 dblp:conf/IEEEpact/SethiaDSM13 fatcat:um6eqwt5o5aglme77m2hvcmxx4

Memory-centric system interconnect design with Hybrid Memory Cubes

Gwangsun Kim, John Kim, Jung Ho Ahn, Jaeha Kim
2013 Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques  
As a result, the HMC (Hybrid Memory Cube) has recently been proposed to improve DRAM bandwidth as well as energy efficiency. In this paper, we explore different system interconnect designs with HMCs.  ...  Memory bandwidth has been one of the most critical system performance bottlenecks.  ...  CONCLUSIONS In this work, we explored a system interconnect design that leverages the hybrid memory cubes (HMCs).  ... 
doi:10.1109/pact.2013.6618812 dblp:conf/IEEEpact/KimKAK13 fatcat:msleo2kuejezjg5xba3p65pamm

ALPHA: A Hybrid Topology for Memory-centric Network

Jiaxiang Li, Huaxi Gu, Shixiong Qi, Haoran Wang, Kang Wang
2019 IEICE Electronics Express  
Memory-centric network (MCN) is considered as a promising candidate for future system interconnect.  ...  To improve the energyefficiency of memory access system by utilizing MCN, the topology of MCN needs to be carefully designed, as interconnection links take a huge part of power consumption.  ...  Meanwhile, with the emerging of new DRAM devices, such as Hybrid Memory Cube (HMC) [6] , the implementation of MCN tends to be possible.  ... 
doi:10.1587/elex.16.20181108 fatcat:l5pqtppcrfcgfdkwl6tvs4qmru

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube

Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
2017 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power  ...  In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) in  ...  internal to the memory-centric network.  ... 
doi:10.1109/tvlsi.2016.2570283 fatcat:y5e5bddh7fhljdbsxwmkjl73qa

A Novel Decomposed Optical Architecture for Satellite Terrestrial Network Edge Computing

Xiaotao Guo, Ying Zhang, Yu Jiang, Shenggang Wu, Hengnian Li
2022 Mathematics  
Experimental validation of the decomposed computing network prototype employs a four-port NOS to interconnect four processor/memory cubes.  ...  An output OSNR of up to 30.5 dB and an none-error transmission with 1.5 dB penalty is obtained when scaling the NOS port count to 64.  ...  The on-board resource of the memory cubes is based on the Double Data Rate 4 (DDR4) memory or Hybrid Memory Cube (HMC), connected to the memory controller (resource management module of memory cube).  ... 
doi:10.3390/math10142515 fatcat:7xxtfv4e6vfj5h3ho4dsrsf64q

The Machine

Kimberly Keeton
2015 Proceedings of the 5th International Workshop on Runtime and Operating Systems for Supercomputers - ROSS '15  
• Local memory provides lower-latency, higher- bandwidth performance tier Example: Micron's Hybrid Memory Cube (HMC) Source: Micron Source: J.  ...  Implications for memory-centric operating systems P. Faraboschi, K. Keeton, T. Marsland, D. Milojicic, "Beyond processor-centric operating systems," Proc.  ...  Naïve implementation: The Atlas programming model • Memory is shared − Shared datasets permit low overhead work stealing -potential solution to static load balancing challenges − Shared data structures  ... 
doi:10.1145/2768405.2768406 dblp:conf/hpdc/Keeton15 fatcat:ritr3meabfccrj4j5k2eia45va

A Classification of Memory-Centric Computing

Hoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui, Francky Catthoor
2020 ACM Journal on Emerging Technologies in Computing Systems  
For example, Hybrid Memory Cube is considered to be near-memory-computing [100], however, it is also referred to as processor-in-memory [3] .  ...  With these distinct metrics, the classification covers all computing architectures in general and memory-centric computing in specific.  ...  In case the memory contains additional logic circuits such as in Hybrid Memory Cubes (HMC) [100] , we speak of a System in Package (SiP).  ... 
doi:10.1145/3365837 fatcat:n5cipv6h5vheppoa6krd5qmv7i

Near-Data Processing: Insights from a MICRO-46 Workshop

Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime H. Moreno, Richard Murphy, Ravi Nair, Steven Swanson
2014 IEEE Micro  
In contrast, in the data-centric model, data lives in different storage levels within the hierarchy, with processing engines surrounding the data and operating on such data without moving it across the  ...  in large-scale systems is shifting from the traditional computingcentric model successfully used for many decades into one that is more data centric.  ...  new opportunities for NDP-customized interconnect designs. 7.  ... 
doi:10.1109/mm.2014.55 fatcat:sm7nqssporhd3bfa2srmklou64

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Gagandeep Singh, Lorenzo Chelini, Stefano Corda, Ahsan Javed Awan, Sander Stuijk, Roel Jordans, Henk Corporaal, Albert-Jan Boonstra
2018 2018 21st Euromicro Conference on Digital System Design (DSD)  
We highlight the challenges as well as the critical need of evaluation methodologies that can be employed in designing these special architectures.  ...  At the same time, the advancement in integration technologies have made the decade-old concept of coupling compute units close to the memory (called Near-Memory Computing) more viable.  ...  A hybrid design can revolutionize our current systems.  ... 
doi:10.1109/dsd.2018.00106 dblp:conf/dsd/SinghCCASJCB18 fatcat:26ucg3klobahff5mguj25lh44m

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Liang Chang, Chenglong Li, Zhaomin Zhang, Jianbiao Xiao, Qingsong Liu, Zhen Zhu, Weihang Li, Zixuan Zhu, Siqi Yang, Jun Zhou
2021 Science China Information Sciences  
Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM).  ...  However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture.  ...  [12] proposed a Terasys system equipped with a designed and fabricated processor-in-memory processor chip.  ... 
doi:10.1007/s11432-021-3234-0 fatcat:np7wtg24rzavbc5fsmammikn3i

A Survey of Different Approaches for Overcoming the Processor - Memory Bottleneck

Danijela Efnusheva, Ana Cholakoska, Aristotel Tentov
2017 International Journal of Computer Science & Information Technology (IJCSIT)  
Within this analysis we discuss the advantages, disadvantages and the application (purpose) of several well-known memory-centric systems.  ...  The reason for this resides in the well known Von-Neumann bottleneck problem which occurs during the communication between the processor and the main memory into a standard processor-centric system.  ...  memory cube (places several memory modules dies on top of each other in a 3D cube shape) and embedded DRAM (eDRAM is integrated on the same chip die with the processor), [23] , [32] - [35] .  ... 
doi:10.5121/ijcsit.2017.9214 fatcat:u6gztzqgyzam3np5fdyzd2sotu

Multi-GPU System Design with Memory Networks

Gwangsun Kim, Minseok Lee, Jiyun Jeong, John Kim
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
GPUs are being widely used to accelerate different workloads and multi-GPU systems can provide higher performance with multiple discrete GPUs interconnected together.  ...  In order to overcome the communication limitations, we propose to leverage the memory network based on hybrid memory cubes (HMCs) to simplify multi-GPU memory management and improve programmability.  ...  Network Characteristic Prior system interconnect design with hybrid memory cubes (HMCs) [5] for a multi-CPU system is not necessarily optimal for multi-GPU systems.  ... 
doi:10.1109/micro.2014.55 dblp:conf/micro/KimLJK14 fatcat:e6mrhqrbjze4bodcplfwnemg54

Data Movement Options in Accelerated Clusters [chapter]

Holger Fröning
2014 Lecture Notes in Computer Science  
transition to communication-centric systems composed of heterogeneous computing units.  ...  The modern GPUs memory respectively system interface coalesces these fine-grain accesses into bulk transfers. These accesses are intercepted by a network device with appropriate support.  ...  Also, Lena Oden and Benjamin Klenk have contributed with discussions to many insights and performed numerous experiments.  ... 
doi:10.1007/978-3-642-54420-0_41 fatcat:uv4srhx4tvgj5kccf4cvbbim7q

Enabling Practical Processing in and near Memory for Data-Intensive Computing [article]

Onur Mutlu, Saugata Ghose, Juan Gómez-Luna, Rachata Ausavarungnirun
2019 arXiv   pre-print
memory technology design to provide high bandwidth to in-memory logic.  ...  parts of the system are dedicated to.  ...  Fundamentally solving the data movement problem requires a paradigm shift to a data-centric computing system design, where computation happens in or near memory, with minimal data movement.  ... 
arXiv:1905.04376v1 fatcat:3hrtdczkrbgvxo364whfdr2tci

ReGra: Accelerating Graph Traversal Applications Using ReRAM with Lower Communication Cost

Haoqiang Liu, Qiang-Sheng Hua, Hai Jin, Long Zheng
2020 IEEE Access  
INDEX TERMS Processing-in-memory, resistive memory, ReRAM, architecture, communication.  ...  There is a growing gap between data explosion speed and the improvement of graph processing systems on conventional architectures.  ...  All of the ReRAM crossbar cubes are interconnected in a memory-centric network [19] . The topology among memory cubes is dragonfly offering higher bandwidth and throughput.  ... 
doi:10.1109/access.2020.3003982 fatcat:2fedobijqjatfkkdnwdd67ldqe
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