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Memory-Efficient Performance Monitoring on Programmable Switches with Lean Algorithms [article]

Zaoxing Liu, Samson Zhou, Ori Rottenstreich, Vladimir Braverman, Jennifer Rexford
2019 arXiv   pre-print
We implement prototypes of our lean algorithms on a commodity programmable switch using the P4 language.  ...  Instead, we propose sketch-based performance monitoring using memory that is sublinear in the number of flows. Existing sketches estimate flow monitoring metrics based on flow sizes.  ...  To this end, we ask can we build a performance monitoring tool with high accuracy that is memory-efficient? DEFINITION 1.  ... 
arXiv:1911.06951v1 fatcat:wcayufvegjcubbl5lfujtsdzsq

LEAN

Jeff Huang, Charles Zhang
2012 Proceedings of the ACM international conference on Object oriented programming systems languages and applications - OOPSLA '12  
Our evaluation results with several real world concurrency bugs in large complex server programs demonstrate that LEAN is able to reduce the size, the number of threads, and the number of thread context  ...  We present a new technique, LEAN, on top of replay, that significantly reduces the complexity of the replay trace and the length of the replay time without losing the determinism in reproducing concurrency  ...  Moreover, all the instrumentations and the thread scheduler in LEAN are transparent to the programmers, such that the debugging task can be performed on the simplified buggy execution in a normal debugging  ... 
doi:10.1145/2384616.2384649 dblp:conf/oopsla/HuangZ12 fatcat:hxhjowmgz5avvbvamf3sba6hai

LEAN

Jeff Huang, Charles Zhang
2012 SIGPLAN notices  
Our evaluation results with several real world concurrency bugs in large complex server programs demonstrate that LEAN is able to reduce the size, the number of threads, and the number of thread context  ...  We present a new technique, LEAN, on top of replay, that significantly reduces the complexity of the replay trace and the length of the replay time without losing the determinism in reproducing concurrency  ...  Moreover, all the instrumentations and the thread scheduler in LEAN are transparent to the programmers, such that the debugging task can be performed on the simplified buggy execution in a normal debugging  ... 
doi:10.1145/2398857.2384649 fatcat:r5xybnelkfeznfy2tuyihuqqyu

Dynamic hardware/software partitioning

Greg Stitt, Roman Lysecky, Frank Vahid
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded  ...  We describe our system architecture and initial onchip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic  ...  However, our profiler is non-intrusive, working by monitoring instruction addresses on the memory bus.  ... 
doi:10.1145/775894.775896 fatcat:vqt6jeltpbdkrlmm7wuxxlyjq4

Dynamic hardware/software partitioning

Greg Stitt, Roman Lysecky, Frank Vahid
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded  ...  We describe our system architecture and initial onchip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic  ...  However, our profiler is non-intrusive, working by monitoring instruction addresses on the memory bus.  ... 
doi:10.1145/775832.775896 dblp:conf/dac/StittLV03 fatcat:gxuxvphsuzcn7j3xspmjcrt4eu

NanoStreams: Codesigned microservers for edge analytics in real time

Giorgis Georgakoudis, Charles Gillan, Ahmad Hassan, Umar I. Minhas, Ivor Spence, George Tzenakis, Hans Vandierendonck, Roger Woods, Dimitrios S. Nikolopoulos, Murali Shyamsundar, Paul Barber, Matthew Russell (+8 others)
2016 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)  
Packets can be switched via Ethernet switches, however, HAT provides the ability to further customise the Ethernet header for efficiency, when switching is not required.  ...  Additionally, we make use of on-board IPMI power monitoring sensors with a sampling frequency of 4 Hz.  ... 
doi:10.1109/samos.2016.7818346 dblp:conf/samos/GeorgakoudisGHM16 fatcat:d7ljernsljftzc6s64a54z53cy

A Survey on Data Plane Programming with P4: Fundamentals, Advances, and Applied Research [article]

Frederik Hauser, Marco Häberle, Daniel Merling, Steffen Lindner, Vladimir Gurevich, Florian Zeiger, Reinhard Frank, Michael Menth
2021 arXiv   pre-print
Programmable data planes allow users to define their own data plane algorithms for network devices including appropriate data plane application programming interfaces (APIs) which may be leveraged by user-defined  ...  Finally, we discuss potential next steps based on our findings.  ...  [222] use sketches for performance monitoring. They introduce lean algorithms to measure metrics like loss or out-of-order packets.  ... 
arXiv:2101.10632v3 fatcat:ci4hkca5ibdzpatgowhzqcqzvm

Runtime Programmable Switches

Jiarong Xing, Kuo-Feng Hsu, Matty Kadosh, Alan Lo, Yonatan Piasetzky, Arvind Krishnamurthy, Ang Chen
2022 Symposium on Networked Systems Design and Implementation  
Our evaluation results demonstrate the feasibility and benefits of runtime programmable switches.  ...  FlexCore enables partial reconfiguration of switch data planes at runtime with minimum resource overheads, without service disruption, while processing packets with consistency guarantees.  ...  Runtime Reconfiguration Algorithms The FlexCore reconfiguration algorithms rely on the partial reconfiguration primitives to transform an existing switch program prog to a new one prog * .  ... 
dblp:conf/nsdi/XingHKLPKC22 fatcat:ebbojq7ahzeo3hodlwpbq5o4b4

Low Power Operating System for Heterogeneous Wireless Communication System [chapter]

Suet-Fei Li, Roy Sutton, Jan Rabaey
2003 Compilers and Operating Systems for Low Power  
The proposed novel hybrid approach to system power management combines distributed power control with global monitoring.  ...  Preliminary results indicate that the event-driven OS achieves an 8x improvement in performance, 2x and 30x improvement in instruction and data memory requirement, and a 12x reduction in power over its  ...  Global monitoring is added to further improve the system performance via feedback derived from observations with greater system scope.  ... 
doi:10.1007/978-1-4419-9292-5_1 fatcat:ryo6dcbv7nbhnm73euw4j7sxuu

Enabling In-situ Programmability in Network Data Plane: From Architecture to Language

Yong Feng, Zhikang Chen, Haoyu Song, Wenquan Xu, Jiahao Li, Zijian Zhang, Tong Yun, Ying Wan, Bin Liu
2022 Symposium on Networked Systems Design and Implementation  
The compiler contains algorithms to support efficient resource mapping for both base design and incremental updates.  ...  To manifest the in-situ programming feasibility, we demonstrate several practical use cases on both a software switch, ipbm, and an FPGA-based prototype.  ...  Trial on new protocols/algorithms.  ... 
dblp:conf/nsdi/FengC0XLZYW022 fatcat:zjjoiqfr7berjkutafga4bmmzu

Digital Learning Controller Design for the Booster Ring AC Power Supplies in Taiwan Photon Source

Yuanchen Chien, Chenyao Liu, Yongseng Wong, Kuobin Liu, Baosheng Wang
2017 Innovative Computing Information and Control Express Letters, Part B: Applications  
Here we propose a hybrid iterative learning control (ILC) algorithm combined with discrete PID feedback controller with the objective to minimize the tracking error with iterative learning automatically  ...  The performance requirement is much stricken particularly in the AC mode.  ...  In the FPGA, P-type ILC control block, discrete PID controller and PWM algorithm are implemented. In addition, the block memories in the FPGA are utilized as the parameter memories for ILC.  ... 
doi:10.24507/icicelb.08.05.827 fatcat:kqahyncusjgd3cteyrat2oe3xq

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
Our design implements fast queueing through an application's address space with operations that are compatible with a fully software queue.  ...  HAQu adds hardware to a CMP that accelerates operations on software queues.  ...  However, some applications perform better with dynamic load balancing algorithms.  ... 
doi:10.1109/hpca.2011.5749720 dblp:conf/hpca/LeeTST11 fatcat:devdykb66zenvc5bsbenh4bkmy

Warp Processors

Roman Lysecky, Greg Stitt, Frank Vahid
2006 ACM Transactions on Design Automation of Electronic Systems  
with minimal computation time and data memory so as to coexist on chip with the main processor.  ...  We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology  ...  Instead, we incorporate a nonintrusive profiler that monitors the instruction addresses seen on the instruction memory bus [Gordon-Ross and Vahid 2003] .  ... 
doi:10.1145/1142980.1142986 fatcat:sqcy36iw7neqlnmyzvwriwrequ

A survey of sketches in traffic measurement: Design, Optimization, Application and Implementation [article]

Shangsen Li, Lailong Luo, Deke Guo, Qianzhen Zhang, Pengtao Fu
2021 arXiv   pre-print
Then the space-efficient sketches from the distributed measurement nodes are aggregated to provide statistics of the undergoing flows.  ...  Currently, tremendous redesigns and optimizations have been proposed to improve the sketches for better network measurement performance.  ...  HashPipe [137] is an algorithm for tracking the k heaviest flows with high accuracy within the features and constraints of programmable switches.  ... 
arXiv:2012.07214v2 fatcat:lme2ghsshje3tag2m5q3xgvcna

An adaptive system-on-chip for network applications

R. Koch, T. Pionteck, C. Albrecht, E. Maehle
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
With reference to a prototypical implementation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues.  ...  The system-onchip architecture is based on an adaptable network-onchip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure.  ...  This work was funded in part by the German Research Foundation (DFG) within priority programme 1148 under grant reference Ma 1412/5.  ... 
doi:10.1109/ipdps.2006.1639445 dblp:conf/ipps/KochPAM06 fatcat:bumorkprabcenkrm6i55udaqpu
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