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Memory Requirement Reduction of Deep Neural Networks Using Low-bit Quantization of Parameters [article]

Niccoló Nicodemo and Gaurav Naithani and Konstantinos Drossos and Tuomas Virtanen and Roberto Saletti
<span title="2019-11-01">2019</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Effective employment of deep neural networks (DNNs) in mobile devices and embedded systems is hampered by requirements for memory and computational power.  ...  The application of the low-bit quantization allows a 50% reduction of the DNN memory footprint while the STOI performance drops only by 2.7%.  ...  Memory Requirement Reduction of Deep Neural Networks Using Low-bit Quantization of Parameters  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1911.00527v1">arXiv:1911.00527v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/vvrqusiyirft7j6qrfn677priy">fatcat:vvrqusiyirft7j6qrfn677priy</a> </span>
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A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing

Mário P. Véstias
<span title="2019-07-31">2019</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/63zsvf7vxzfznojpqgfvpyk2lu" style="color: black;">Algorithms</a> </i> &nbsp;
The convolutional neural network (CNN) is one of the most used deep learning models for image detection and classification, due to its high accuracy when compared to other machine learning algorithms.  ...  CNNs achieve better results at the cost of higher computing and memory requirements. Inference of convolutional neural networks is therefore usually done in centralized high-performance platforms.  ...  These include CPUs (Central Processing Unit), GPUs (Graphics Processing Unit), DSPs (Digital Signal Processor), FPGAs (Field-Programmable Gate Array), ASICs (Applications Specific Integrated Circuit),  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/a12080154">doi:10.3390/a12080154</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jbdak7eisbcjtj6ba5hlpvnq5y">fatcat:jbdak7eisbcjtj6ba5hlpvnq5y</a> </span>
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Scaling for edge inference of deep neural networks

Xiaowei Xu, Yukun Ding, Sharon Xiaobo Hu, Michael Niemier, Jason Cong, Yu Hu, Yiyu Shi
<span title="">2018</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/os5ykwallzhl5hodsq5ybyeq74" style="color: black;">Nature Electronics</a> </i> &nbsp;
Graphics processing units (GPUs), field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are popular hardware platforms for accommodating networks for edge inference  ...  A clear trend in deep neural networks is the exponential growth of network size and the associated increases in computational complexity and memory consumption.  ...  Quantized neural networks 88 , binarized neural networks 95 and XNOR-net 92 achieved a large reduction in memory/computation cost by reducing the weights to only 1 bit and the activations to 1-2 bits  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1038/s41928-018-0059-3">doi:10.1038/s41928-018-0059-3</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/g6oezqmezbhcjbli6pxbvnrihm">fatcat:g6oezqmezbhcjbli6pxbvnrihm</a> </span>
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FPGA Implementation for Odor Identification with Depthwise Separable Convolutional Neural Network

Zhuofeng Mo, Dehan Luo, Tengteng Wen, Yu Cheng, Xin Li
<span title="2021-01-27">2021</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/taedaf6aozg7vitz5dpgkojane" style="color: black;">Sensors</a> </i> &nbsp;
In this article, we propose a method for implementing a deep neural network for odor identification in a small-scale Field-Programmable Gate Array (FPGA).  ...  The integrated electronic nose (e-nose) design, which integrates sensor arrays and recognition algorithms, has been widely used in different fields.  ...  It can be noticed that the convolutional layer parameters of an OIDSCNN requires 1600 bits of memory, where a CNN requires 10,112 bits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/s21030832">doi:10.3390/s21030832</a> <a target="_blank" rel="external noopener" href="https://www.ncbi.nlm.nih.gov/pubmed/33513692">pmid:33513692</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/73i3v2fgabhovf5vn2pkhulkoe">fatcat:73i3v2fgabhovf5vn2pkhulkoe</a> </span>
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Accelerating Deep Neural Networks implementation: A survey

Meriam Dhouibi, Ahmed Karim Ben Salem, Afef Saidi, Slim Ben Saoud
<span title="2021-03-10">2021</span> <i title="Institution of Engineering and Technology (IET)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/34xrdbeizvba5cnrxymhir5cxi" style="color: black;">IET Computers &amp; Digital Techniques</a> </i> &nbsp;
Field Programmable Gate Arrays (FPGAs) are promising platforms for the deployment of large-scale DNN which seek to reach a balance between the above objectives.  ...  Deploying such Deep Neural Networks (DNN) on embedded devices is still a challenging task considering the massive requirement of computation and storage.  ...  Network (RNN) including Long Short-Term Memory (LSTM) and Gated Recurrent Units (GRU), Generative Adversarial Network (GAN), Deep Reinforcement Learning (DRL), etc.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/cdt2.12016">doi:10.1049/cdt2.12016</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3kl4j5ztl5eahmgv7vetu2egay">fatcat:3kl4j5ztl5eahmgv7vetu2egay</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210715065134/https://ietresearch.onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cdt2.12016" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5a/a1/5aa18352e17f23f63401fee5f83832e6f7fad537.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/cdt2.12016"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Approximation Computing Techniques to Accelerate CNN Based Image Processing Applications – A Survey in Hardware/Software Perspective

Manikandan N
<span title="2020-06-25">2020</span> <i title="The World Academy of Research in Science and Engineering"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/naqzxq5hurh2bp2pnvwitnnx44" style="color: black;">International Journal of Advanced Trends in Computer Science and Engineering</a> </i> &nbsp;
for implementation (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)), training or testing phase and results (in terms of accuracy, area, power, throughput, resource  ...  In today's technology era, Convolutional Neural Networks (CNNs) are the limelight for various cognitive tasks because of their high accuracy.  ...  [88] used bit-level XNOR gates and shifting operations to reduce the bottleneck caused by using multipliers for MAC operations and also used data quantization techniques to reduce the memory footprint  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.30534/ijatcse/2020/202932020">doi:10.30534/ijatcse/2020/202932020</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/k3qozwldifeedp5sx5x2o37oyu">fatcat:k3qozwldifeedp5sx5x2o37oyu</a> </span>
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MB-CNN: Memristive Binary Convolutional Neural Networks for Embedded Mobile Devices

Arjun Pal Chowdhury, Pranav Kulkarni, Mahdi Nazm Bojnordi
<span title="2018-10-13">2018</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dsgk7nhfgbdvdpo65fxkqjgjr4" style="color: black;">Journal of Low Power Electronics and Applications</a> </i> &nbsp;
Recent work has shown that binarizing a neural network can significantly improve the memory requirements of mobile devices at the cost of minor loss in accuracy.  ...  This paper proposes MB-CNN, a memristive accelerator for binary convolutional neural networks that perform XNOR convolution in-situ novel 2R memristive data blocks to improve power, performance, and memory  ...  A typical deep convolutional neural network may require millions of parameters to be learned and stored during the training pass and to be retrieved and used for inference.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/jlpea8040038">doi:10.3390/jlpea8040038</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qwrw67tx4ffuthzy5xi4o4ee2y">fatcat:qwrw67tx4ffuthzy5xi4o4ee2y</a> </span>
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Best Practices for the Deployment of Edge Inference: The Conclusions to Start Designing

Georgios Flamis, Stavros Kalapothas, Paris Kitsos
<span title="2021-08-09">2021</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a> </i> &nbsp;
The training phase is executed with the use of 32-bit floating point arithmetic as this is the convenient format for GPU platforms.  ...  During training, all the weights are calculated through optimization and back propagation of the network.  ...  In the state-of-the-art for accelerating deep learning algorithms a plethora of hardware platforms are supported such as, field programmable gate array (FPGA), application specific integrated circuit (  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics10161912">doi:10.3390/electronics10161912</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3ywb6inqzvbfxb2vjve6ffvmiq">fatcat:3ywb6inqzvbfxb2vjve6ffvmiq</a> </span>
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A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference

Arnab Neelim Mazumder, Jian Meng, Hasib-Al Rashid, Utteja Kallakuri, Xin Zhang, Jae-sun Seo, Tinoosh Mohsenin
<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cuk7yvxow5gknlxza65us4b7fi" style="color: black;">IEEE Journal on Emerging and Selected Topics in Circuits and Systems</a> </i> &nbsp;
Deep neural networks (DNNs) are being prototyped for a variety of artificial intelligence (AI) tasks including computer vision, data analytics, robotics, etc.  ...  However, this advantage comes from the high computational complexity of the DNNs in use.  ...  However, when considering frameworks like micro-controllers, memoryconstrained drones, low power edge devices, and small field programmable gate arrays (FPGAs), these bulky AI models do not suit the deployment  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jetcas.2021.3129415">doi:10.1109/jetcas.2021.3129415</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nknpy4eernaeljz2hpqafe7sja">fatcat:nknpy4eernaeljz2hpqafe7sja</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220107015545/https://ieeexplore.ieee.org/ielx7/5503868/9647029/09627710.pdf?tp=&amp;arnumber=9627710&amp;isnumber=9647029&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0a/a6/0aa621e8785a85738ef97b491fbe55675a4b1ae0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jetcas.2021.3129415"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A Survey on Efficient Convolutional Neural Networks and Hardware Acceleration

Deepak Ghimire, Dayoung Kil, Seong-heum Kim
<span title="2022-03-18">2022</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a> </i> &nbsp;
The learning capability of convolutional neural networks (CNNs) originates from a combination of various feature extraction layers that fully utilize a large amount of data.  ...  However, they often require substantial computation and memory resources while replacing traditional hand-engineered features in existing systems.  ...  Acknowledgments: We appreciate our reviewers and editors for their precious time in providing valuable comments and improving our paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics11060945">doi:10.3390/electronics11060945</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bxxgccwkujatzh4onkzh5lgspm">fatcat:bxxgccwkujatzh4onkzh5lgspm</a> </span>
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INsight: A Neuromorphic Computing System for Evaluation of Large Neural Networks [article]

Jaeyong Chung, Taehwan Shin, Yongshin Kang
<span title="2015-08-05">2015</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
We demonstrate an implementation of the neuromorphic computing system based on a field-programmable gate array that performs the MNIST hand-written digit classification with 97.64% accuracy.  ...  This paper describes a neuromorphic computing system that is designed from the ground up for the energy-efficient evaluation of large-scale neural networks.  ...  Until today, the man-made information processing device at the lowest power consumption is application-specific integrated circuits (ASICs) and, for general purpose, field programmable gate arrays (FPGAs  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1508.01008v1">arXiv:1508.01008v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/noi45s26vfbdnoqpn42cgxjqba">fatcat:noi45s26vfbdnoqpn42cgxjqba</a> </span>
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CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration with Better-than-Binary Energy Efficiency [article]

Moritz Scherer, Georg Rutishauser, Lukas Cavigelli, Luca Benini
<span title="2021-02-04">2021</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
We present a 3.1 POp/s/W fully digital hardware accelerator for ternary neural networks.  ...  , 2) targeting ternary neural networks which, in contrast to binary NNs, allow for sparse weights which reduce switching activity, and 3) introducing an optimized training method for higher sparsity of  ...  This project was supported in part by the EU's H2020 Programme under grant no. 732631 (OPRECOMP).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2011.01713v2">arXiv:2011.01713v2</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wcxxzgr5cfgflm5ix2thcviqlu">fatcat:wcxxzgr5cfgflm5ix2thcviqlu</a> </span>
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MulNet: A Flexible CNN Processor with Higher Resource Utilization Efficiency for Constrained Devices

Muluken Tadesse Hailesellasie, Syed Rafay Hasan
<span title="">2019</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
On the other hand, field-programmable gate arrays (FPGAs) are becoming a promising choice in giving hardware solutions for most deep learning implementations due to their high-performance and low-power  ...  Leveraging deep convolutional neural networks (DCNNs) for various application areas has become a recent inclination of many machine learning practitioners due to their impressive performance.  ...  In terms of hardware platform, Field Programmable Gate Arrays (FPGAs) are becoming the dominating choice for high performance and low-power deep learning processor design [4] - [7] .  ... 
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Hardware Accelerator Design for Machine Learning [chapter]

Li Du, Yuan Du
<span title="2018-09-19">2018</span> <i title="InTech"> Machine Learning - Advanced Techniques and Emerging Applications </i> &nbsp;
Field programmable gate arrays (FPGA) show better energy efficiency compared with GPU when computing machine learning algorithm at the cost of low speed.  ...  kinds of machine learning algorithms such as a deep convolutional neural network.  ...  As the industry matures, field programmable gate arrays (FPGAs) are now starting to emerge as credible competition to GPUs for implementing CNN-based deep learning algorithms.  ... 
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Reduced memory region based deep Convolutional Neural Network detection

Denis Tome, Luca Bondi, Luca Baroffio, Stefano Tubaro, Emanuele Plebani, Danilo Pau
<span title="">2016</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/jogl3uvosbhelhqynauphlyh2y" style="color: black;">2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)</a> </i> &nbsp;
This paper makes two main contributions: (1) it proves that a region based deep neural network can be finely tuned to achieve adequate accuracy for pedestrian detection (2) it achieves a very low memory  ...  Unfortunately, such approaches require vast amounts of computational power and memory, preventing efficient implementations on embedded systems.  ...  However, in a scenario in which a hardware designer can draw on an Application Specific Integrated Circuit (ASIC) or on an Field Programmable Gate Array (FPGA) all the connections between neurons individually  ... 
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