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Distributed-memory parallelization of the aggregated unfitted finite element method [article]

Francesc Verdugo, Alberto F. Martín, Santiago Badia
2019 arXiv   pre-print
While most of previous references discussing linear solvers for unfitted methods are based on serial non-scalable algorithms, we propose a parallel distributed-memory method able to efficiently solve problems  ...  The specific goal of this work is to present the implementation and performance of the method on distributed-memory platforms aiming at the efficient solution of large-scale problems.  ...  successful application of unfitted FE techniques in realistic large-scale applications.  ... 
arXiv:1902.01168v1 fatcat:do5i67jmrbb2xbnxe2f345uefe

Optimizing memory transactions for large-scale programs

Fernando Miguel Carvalho, João Cachopo
2016 Journal of Parallel and Distributed Computing  
My approach and experimental results show that STMs may be the first efficient alternative to locks for shared-memory synchronization in real-world-sized applications.  ...  My proposal is based on Software Transactional Memory (STM) and I implemented it in a well-known STM framework for Java-Deuce STM.  ...  large scale CAD/CAM application.  ... 
doi:10.1016/j.jpdc.2015.12.001 fatcat:qafvg3qxpzclniovsdvt4n3eqe

Analysis, Classification and Comparison of Scheduling Techniques for Software Transactional Memories

Pierangelo Di Sanzo
2017 IEEE Transactions on Parallel and Distributed Systems  
Transactional Memory (TM) is a practical programming paradigm for developing concurrent applications.  ...  After one decade of research, this article reviews the wide variety of scheduling techniques proposed for Software Transactional Memories.  ...  -efficient graph representation, Vacation -travel reservations, and Yada -Delaunay mesh refinement), (iii) STMBench7 [30] , a benchmark derived from CAD/CAM applications, where transactions read and  ... 
doi:10.1109/tpds.2017.2740285 fatcat:yhqcv7gckreidpppl5zxpm3bhm

Generation of distributed logic-memory architectures through high-level synthesis

Chao Huang, S. Ravi, A. Raghunathan, N.K. Jha
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
over another, and utilizes conventional HLS techniques for intermediate steps.  ...  In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in  ...  Paper Overview and Contributions In this work, we present techniques for HLS of distributed logic-memory architectures.  ... 
doi:10.1109/tcad.2005.852276 fatcat:lx7widohlvefjf2xht7vjses5m

Distributed and fault-tolerant computation for retrieval tasks using distributed associative memories

J.M. Char, V. Cherkassy, H. Wechsler, G.L. Zimmerman
1988 IEEE transactions on computers  
Distributed and F ••II-Tolerant Computation for Retrieval Tasks Usial Distributed Associative Memories JOIS MAUnu CHAR. VLADIMIR CHERKASSKY. Fig (20).  ...  CONCLUSIONS We describe in this paper the distributed associative memory (DAM) model for distributed and fault-tolerant computation as related to i~ recognition and database retrieval tasks.  ... 
doi:10.1109/12.2196 fatcat:n2kkebm3xferbipqu4luzidt5q

Distributed-memory parallelization of the aggregated unfitted finite element method

Francesc Verdugo, Alberto F. Martín, Santiago Badia
2019 Computer Methods in Applied Mechanics and Engineering  
While most of previous references discussing linear solvers for unfitted methods are based on serial non-scalable algorithms, we propose a parallel distributed-memory method able to efficiently solve problems  ...  The specific goal of this work is to present the implementation and performance of the method on distributed-memory platforms aiming at the efficient solution of large-scale problems.  ...  The authors thankfully acknowledge the computer resources at Marenostrum-IV and the technical support provided by the Barcelona Supercomputing Center (RES-ActivityID: FI-2018-1-0014, FI-2018-2-0009, FI  ... 
doi:10.1016/j.cma.2019.112583 fatcat:56ncxzrhcfam5ihlgmtp2ql7fq

Co-ordinating Distributed Knowledge: A Study into the Use of an Organisational Memory

M. J. Perry, R. Fruchter, D. Rosenberg
1999 Cognition, Technology & Work  
We argue that understanding how people make use of distributed knowledge is crucial to the design of an organisational memory.  ...  The knowledge and information captured in the organisational memory enabled the team members to establish a common understanding of the design and to gain an appreciation of the issues and concerns of  ...  The study was also carried out whilst the first author was working as a visiting scholar at CSLI (the centre for the study of language and information) at Stanford University.  ... 
doi:10.1007/s101110050012 fatcat:qcnuhczhbfa3xbp77sqi26j53a

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators

Yoshikazu INAGAKI, Shinya TAKAMAEDA-YAMAZAKI, Jun YAO, Yasuhiko NAKASHIMA
2015 IEICE transactions on information and systems  
) is equipped with distributed single-port local memories and ring-formed interconnections.  ...  memory; (3) performance evaluation of the library for PDE solvers.  ...  Acknowledgments This work was supported by JSPS KAKENHI Grant Numbers 24240005 and 24650020.  ... 
doi:10.1587/transinf.2015pap0015 fatcat:us2pqvhtsbbebfanqwhoemhzd4

Automated memory-aware application distribution for Multi-processor System-on-Chips

Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen
2007 Journal of systems architecture  
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time.  ...  The scheme bounds optimization iterations to a reasonable limit and defines an annealing schedule that scales up with application and architecture complexity.  ...  Communication delays for both shared and distributed memory architectures can be modeled as well.  ... 
doi:10.1016/j.sysarc.2007.01.013 fatcat:jkcdhyixtjaehle5yipwt4c63y

CADS: Core-Aware Dynamic Scheduler for Multicore Memory Controllers [article]

Eduardo Olmedo Sanchez, Xian-He Sun
2019 arXiv   pre-print
We introduce Core-Aware Dynamic Scheduler (CADS) for multicore memory controller. CADS uses Reinforcement Learning (RL) to alter its scheduling strategy dynamically at runtime.  ...  Hence, novel memory controllers that consider and adapt to the memory access characteristics, and share memory resources efficiently and fairly are necessary.  ...  Consequently they are rigid in practicality and they work well only for certain sets of applications [27] .  ... 
arXiv:1907.07776v1 fatcat:vvrjpymdxvb7dcrdmzveu75hoe

Using shape distributions to compare solid models

Cheuk Yiu Ip, Daniel Lapadat, Leonard Sieger, William C. Regli
2002 Proceedings of the seventh ACM symposium on Solid modeling and applications - SMA '02  
One significant contribution of our work is the systematic technique for performing consistent, engineering content-based comparisons of CAD models produced by different CAD systems.  ...  First, we show how to extend basic distribution-based techniques to handle CAD data that has been exported to VRML format.  ...  At a fundamental level, Constructive Solid Geometry (CSG) and Boundary Representation models (BRep) serve as a foundation for most modeling systems and applications.  ... 
doi:10.1145/566282.566322 dblp:conf/sma/IpLSR02 fatcat:bj2lcu5rgzgjrjzxd2szu5p2ea

Using shape distributions to compare solid models

Cheuk Yiu Ip, Daniel Lapadat, Leonard Sieger, William C. Regli
2002 Proceedings of the seventh ACM symposium on Solid modeling and applications - SMA '02  
One significant contribution of our work is the systematic technique for performing consistent, engineering content-based comparisons of CAD models produced by different CAD systems.  ...  First, we show how to extend basic distribution-based techniques to handle CAD data that has been exported to VRML format.  ...  At a fundamental level, Constructive Solid Geometry (CSG) and Boundary Representation models (BRep) serve as a foundation for most modeling systems and applications.  ... 
doi:10.1145/566313.566322 fatcat:qffysvkezrhexg3apzgmsew5fa

Toward a technology for organizational memories

A. Abecker, A. Bernardi, K. Hinkelmann, O. Kuhn, M. Sintek
1998 IEEE Intelligent Systems and their Applications  
systems, best-practice databases, and lessonslearned archives.  ...  Our view of an organizational memory grew out of our practical experiences and also conforms well with definitions suggested in the literature: an OM's main function is to enhance the organization's competitiveness  ...  In general, organizational memory cannot be understood as a closed research area of its own; it merely grows out of a pragmatic integration of manifold AI-and other-techniques driven by an ambitious application  ... 
doi:10.1109/5254.683209 fatcat:q6tc64f7zfgzfcq3yizfy7biqq

Concurrency control for distributed cooperative engineering applications

João Coelho Garcia, Paulo Ferreira
2002 Proceedings of the 2002 ACM symposium on Applied computing - SAC '02  
Distributed cooperative engineering applications require consistent and long-term sharing of large volumes of data, which may cause conflicts due to concurrent read/write operations.  ...  Current transactional solutions, even if based on an optimistic approach, do not solve the problem because such applications access shared data for long periods of time performing a large number of read  ...  In PerDiS, during transactions data is mapped in application memory using shared memory between the applications' library and the local server.  ... 
doi:10.1145/508969.508977 fatcat:54pvjsfqojdjpndtx52c4nrwai

Concurrency control for distributed cooperative engineering applications

João Coelho Garcia, Paulo Ferreira
2002 Proceedings of the 2002 ACM symposium on Applied computing - SAC '02  
Distributed cooperative engineering applications require consistent and long-term sharing of large volumes of data, which may cause conflicts due to concurrent read/write operations.  ...  Current transactional solutions, even if based on an optimistic approach, do not solve the problem because such applications access shared data for long periods of time performing a large number of read  ...  In PerDiS, during transactions data is mapped in application memory using shared memory between the applications' library and the local server.  ... 
doi:10.1145/508791.508977 dblp:conf/sac/GarciaF02 fatcat:g5je7t5gbfgsri3oilnbj5qz7e
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