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Improving GPU performance via large warps and two-level warp scheduling
2011
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11
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We show that when combined, our mechanisms improve performance by 19.1% over traditional GPU cores for a wide variety of general purpose parallel applications that heretofore have not been able to fully ...
To accomplish this, we propose two independent ideas: the large warp microarchitecture and two-level warp scheduling. ...
Joao, other HPS members and the anonymous reviewers for their comments and suggestions. Veynu Narasiman was supported by an NVIDIA PhD Fellowship during the early part of this work. ...
doi:10.1145/2155620.2155656
dblp:conf/micro/NarasimanSLMMP11
fatcat:jrvx5ogh55f27isv6icoowgd5m
Privacy-preserving activity scheduling on mobile devices
2011
Proceedings of the first ACM conference on Data and application security and privacy - CODASPY '11
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The privacy of the scheduling operation is paramount to the success of such applications, as often users do not want to share their personal schedules with other users or third-parties. ...
Our novel algorithms take advantage of the homomorphic properties of well-known cryptosystems in order to privately compute common user availabilities. ...
ACKNOWLEDGMENT We would like to thank Sudeep Singh Walia and Praveen Kumar for the implementations, Mathias Humbert, Anthony Durussel and Gianpaolo Perrucci for their constructive input that helped improving ...
doi:10.1145/1943513.1943549
dblp:conf/codaspy/BilogrevicJHAN11
fatcat:sl7syxr6xra2vjwpdogeyewosy
Meetings through the cloud: Privacy-preserving scheduling on mobile devices
2011
Journal of Systems and Software
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In this paper, we propose practical and privacy-preserving solutions for mobile devices to the serverbased scheduling problem. ...
The privacy of the scheduling operation is paramount to the success of such applications, as often users do not want to share their personal schedule details with other users or third-parties. ...
the Nokia Research Center (Lausanne) for supporting this project. ...
doi:10.1016/j.jss.2011.04.027
fatcat:iyce6dychfe5zioygedcxrcq44
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
2012
ACM Transactions on Computer Systems
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Combined with a hierarchical register file, our two-level thread scheduler provides a further reduction in energy by only allocating entries in the upper levels of the register file hierarchy for active ...
We extend prior work by integrating the two approaches into a single evaluation showing the tradeoffs between hardware, software, and hybrid control approaches to managing a hierarchical register file. ...
Acknowledgments We thank the anonymous reviewers and the members of the NVIDIA Architecture Research Group for their comments. ...
doi:10.1145/2166879.2166882
fatcat:cwh624dhdbbcffra6mr6kkorgu
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
2010
2010 International Conference on Field Programmable Logic and Applications
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We show that using a combination of register storage structures, each tailored for values with different lifetimes, provides a reduction in overall area-energy product to 0.69× the area-energy of the baseline ...
The goal of this work is to determine the advantages and disadvantages of different architectural structures for storing values on-chip when optimizing for energy efficiency as well as area. ...
CONCLUSIONS In this paper we have considered numerous different mechanisms for storing values in a CGRA. ...
doi:10.1109/fpl.2010.81
dblp:conf/fpl/EssenPWEH10
fatcat:n6mvwugu4neg3pi5rarczptwwm
Access Adaptive and Thread-Aware Cache Partitioning in Multicore Systems
2018
Electronics
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Moreover, the average speedup of multi-thread ATCP with respect to single-thread LRU is at 1.89. ...
Cache partitioning is a successful technique for saving energy for a shared cache and all the existing studies focus on multi-program workloads running in multicore systems. ...
• All ws k registers share a same value, name it with REGS. • For any private cache way, only one corresponding bit is set among all the wp k registers. • All the wp k registers and REGS have no same ...
doi:10.3390/electronics7090172
fatcat:cvfmmjedhbgkrfwhwpfo4ubjnu
Runtime Parallelization of Static and Dynamic Irregular Array of Array References
2018
International Journal of Engineering & Technology
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For pro ling the runtime information, shared and private data structures are used. ...
To detect the dependencies between footprints and for synchronization of threads at runtime, we use bit level operations. ...
This solution works with a single read or writes indirection references inside a loop. ...
doi:10.14419/ijet.v7i4.6.20452
fatcat:jprxbbpnhjfntmxn7kz4ymf3gq
An efficient key-scheduling and bit shuffling algorithm for image data encryption
2018
ACCENTS Transactions on Information Security
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The reversible process is applied for retrieving the data after encryption for decoding component with the different keys for a single file in many trials. The keys are applied for data decryption. ...
In this dissertation standard encryption algorithm with substitution and the key generation mechanism has been applied through blowfish. ...
doi:10.19101/tis.2018.311003
fatcat:6blsjgr5vrfuthvx5c5uofagxq
Reduce to the Max: A Simple Approach for Massive-Scale Privacy-Preserving Collaborative Network Measurements (Extended Version)
[article]
2011
arXiv
pre-print
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E-SMC supports only simple computations with private input and public output, i.e., it can not handle secret input nor secret (intermediate) output. ...
This is achieved by combining a E-SMC scheme with data structures like Bloom Filters and bitmap strings. ...
. , h k with range 1, . . . , m. For each element x ∈ S, the bits hi(x) are set to 1 for 1 ≤ i ≤ k. ...
arXiv:1101.5509v1
fatcat:6g37vrpnq5as3h45cbmngqfe7a
A Comparison for Secured Transmission of Packets in Wireless LAN Using AES and ECC
2013
IOSR Journal of Computer Engineering
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The proposed system uses weighted fair scheduling with Advanced Encryption Standard (AES) for obtaining optimal fragment size and also used Elliptical curve cryptography (ECC) instead of AES to show that ...
Here we introduce a new scheme called Aggregation with Fragment Retransmission (AFR). ...
The objective behind this work was to develop a fair scheduling MAC protocol for a wireless LAN with the following properties: i) The protocol must be fully distributed in that no single node should have ...
doi:10.9790/0661-0925660
fatcat:5jas4s6zdfdltj6numw32z47lu
HIPPI-6400 technology dissemination
1996
Broadband Access Systems
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The first section of the report introduces HIPPI-6400 to familiarize the reader with basic concepts and lay groundwork for future sections. ...
, or usefulness of any information, apparatus, product, or process disdosed, or represents that its use would not infringe privately owned rights. ...
A transmission sequence (TSEQ) value is sent with each micropacket and is returned as a receive sequence (RSEQ) value for correctly received micropackets in the reverse direction control information from ...
doi:10.1117/12.257349
fatcat:txvhy5mjqjblbk5udszwktsbhq
Implementation of Hybrid Cryptosystem using AES-256 and SHA-2 256 by LabVIEW
2017
IJARCCE
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The idea of the proposed Hybrid Cryptosystem is to use the SHA-256 bit as a key generation for AES-256 in order to improve the data security to a greater extent because it provides higher security in terms ...
And from these results we see that the output results will be the same for the compelete hybrid cryptosystem in the two cases. ...
The public key is for encryption, and the private key is used to decrypt the encrypted message which can be only used by the corresponding private key. ...
doi:10.17148/ijarcce.2017.6169
fatcat:pi7gjdjejfhhbfsrgszbrcmz7e
Memory and Energy Optimization Strategies for Multithreaded Operating System on the Resource-Constrained Wireless Sensor Node
2014
Sensors
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With these mechanisms, the stack memory cost of LiveOS can be reduced more than 50% if compared to that of a traditional multithreaded OS. ...
In addition to the stack-shifting dynamic allocation approach, the hybrid scheduling mechanism which can decrease both the thread scheduling overhead and the thread stack number is also implemented in ...
Currently, most WSN nodes are single-core architecture. The single-core node needs to fall asleep during the idle period (for energy conservation, "sleep/wakeup" mechanism, Section 2). ...
doi:10.3390/s150100022
pmid:25545264
pmcid:PMC4327005
fatcat:37hwrqutzff5fiq2defvi3zybe
A light-weight fairness mechanism for chip multiprocessor memory systems
2009
Proceedings of the 6th ACM conference on Computing frontiers - CF '09
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However, the current proposals for fair memory systems are complex as they require an interference measurement mechanism and a fairness enforcement policy for all hardware-controlled shared units. ...
When fairness is chosen as the metric of interest and we compare to a state-of-the-art fairness-aware memory system, DMHA improves fairness by 26% on average with the single program baseline. ...
ACKNOWLEDGEMENTS We extend our gratitude to Marius Grannaes and the anonymous reviewers for valuable comments on earlier versions of this paper. ...
doi:10.1145/1531743.1531747
dblp:conf/cf/JahreN09
fatcat:7gokovt5bfg3jcazorgqnpuqc4
PriFi
2016
Proceedings of the 2016 ACM on Workshop on Privacy in the Electronic Society - WPES'16
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We also propose a technique for protecting against equivocation attacks, with which a malicious relay might de-anonymize clients. ...
Popular anonymity mechanisms such as Tor [4] provide low communication latency but are vulnerable to traffic analysis attacks that can de-anonymize users. ...
Generate an -bit pseudorandom pad p ij for each server S j using a PRG seeded with r ij ; b. Let π denote the permutation generated by the scheduling phase, and x i denote C i 's next bits of data. ...
doi:10.1145/2994620.2994623
fatcat:33qcwzpj5nas3n577sga2yxoae
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