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Measuring the Impact of Memory Errors on Application Performance

Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta
2017 IEEE computer architecture letters  
Prior work has focused on the performance overheads of memory fault-tolerance schemes when errors do not occur at all, and when detected but uncorrectable errors occur, which result in machine downtime  ...  Our analyses of the memory error-reporting stack reveals architecture, firmware, and software opportunities to improve performance consistency by mitigating the worst-case behavior on faulty hardware.  ...  the performance impact of memory errors.  ... 
doi:10.1109/lca.2016.2599513 fatcat:lmnmtq2zdjdm5fak2zaieyzjsi

The application slowdown model

Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, Onur Mutlu
2015 Proceedings of the 48th International Symposium on Microarchitecture - MICRO-48  
and that copies bear this notice and the full citation on the first page.  ...  Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage  ...  Acknowledgments We thank the anonymous reviewers for their feedback. We acknowledge members of the SAFARI research group for their feedback.  ... 
doi:10.1145/2830772.2830803 dblp:conf/micro/SubramanianSGKM15 fatcat:5mhxuhpjcnaglapljvasy2mftq

Classifying soft error vulnerabilities in extreme-Scale scientific applications using a binary instrumentation tool

Dong Li, Jeffrey S. Vetter, Weikuan Yu
2012 2012 International Conference for High Performance Computing, Networking, Storage and Analysis  
how soft errors impact applications.  ...  Extreme-scale scientific applications are at a significant risk of being hit by soft errors on supercomputers as the scale of these systems and the component density continues to increase.  ...  This research is sponsored in part by an NSF award CNS-1059376, and by the Office of Advanced Scientific Computing Research in the U.S. Department of Energy.  ... 
doi:10.1109/sc.2012.29 dblp:conf/sc/LiVY12 fatcat:c6z3n655f5cbzddmfvi5f2fsly

PPT-SASMM: Scalable Analytical Shared Memory Model: Predicting the Performance of Multicore Caches from a Single-Threaded Execution Trace [article]

Atanu Barai, Gopinath Chennupati, Nandakishore Santhi, Abdel-Hameed Badawy, Yehia Arafa, Stephan Eidenbenz
2021 arXiv   pre-print
SASMM can predict the performance of parallel applications running on a multicore.  ...  The profiles are calculated from the memory traces of applications that run sequentially rather than using multi-threaded traces.  ...  The authors would also like to thank Dr. David Newsom for donating several machines to the PEARL laboratory at NMSU. Some of the experiments in this paper were run on the donated machines.  ... 
arXiv:2103.10635v1 fatcat:rijjcrwmhjhwxph5d7y5zzw5sy

Relationship Between the King-Devick Test and Commonly Used Concussion Tests at Baseline

James R. Clugston, Zachary M. Houck, Breton M. Asken, Jonathan K. Boone, Anthony P. Kontos, Thomas A. Buckley, Julianne D. Schmidt, Sara P. D. Chrisman, Nicole L. Hoffman, Kimberly G. Harmon, Thomas W. Kaminski, Michael W. Collins (+4 others)
2019 Journal of athletic training  
Main Outcome Measure(s) Participants completed baseline assessments on the KD and (1) the Symptom Inventory of the Sports Concussion Assessment Tool–3rd edition, (2) the Brief Symptom Inventory-18, (3)  ...  the Balance Error Scoring System, (4) the Standardized Assessment of Concussion (SAC), (5) the Immediate Post-Concussion Assessment and Cognitive Testing (ImPACT) test battery, and (6) the Vestibular/  ...  ACKNOWLEDGMENTS This publication was made possible, in part, by support from the Grand Alliance  ... 
doi:10.4085/1062-6050-455-18 pmid:31584854 pmcid:PMC6922559 fatcat:66iv6fphgbf4vo75rwtjj4antu

Modeling the Impact of Reduced Memory Bandwidth on HPC Applications [chapter]

Ananta Tiwari, Anthony Gamst, Michael A. Laurenzano, Martin Schulz, Laura Carrington
2014 Lecture Notes in Computer Science  
An unfortunate consequence of such designs is that the memory bandwidth per core will be significantly reduced, which can significantly degrade the performance of many memory-intensive HPC workloads.  ...  We apply our framework to a number of large scale HPC applications, observing that the bandwidth sensitivity model shows an absolute mean error that averages less than 5%.  ...  Part of this work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344.  ... 
doi:10.1007/978-3-319-09873-9_6 fatcat:y6fksbpk5rdyveccp5vilfqyte

Application-specific memory protection policies for energy-efficient reliable design

Sheng Yang, Rishad A. Shafik, Saqib Khursheed, David Flynn, Geoff V. Merrett, Bashir M. Al-hashimi
2015 2015 International Symposium on Rapid System Prototyping (RSP)  
In this paper, we show that the vulnerability of memory components due to data retention in the presence of soft errors exhibit orders of magnitude variations with applications through extensive analysis  ...  Using this framework the proposed design flow is validated through extensive number of application case studies based on ARMv7 processors modeled in GEM5.  ...  Figure 5 shows the N vuln of memory components measured across various benchmark applications. It can be seen that the reliability of each memory component varies with application.  ... 
doi:10.1109/rsp.2015.7416541 dblp:conf/rsp/YangSKFMA15 fatcat:wxndh7x2pbeajn5e6qzotmnl3y

Resolving the memory bottleneck for single supply near-threshold computing

Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC).  ...  Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-V t voltage level as the digital logic.  ...  We complete this paper by a study on the impact of future technologies on NTC memories (Section VI). II.  ... 
doi:10.7873/date.2014.215 dblp:conf/date/GemmekeSSRCA14 fatcat:jyssamrjhfffhmjidbhmz5jypi

Sizeless: Predicting the optimal size of serverless functions [article]

Simon Eismann, Long Bui, Johannes Grohmann, Cristina L. Abad, Nikolas Herbst, Samuel Kounev
2021 arXiv   pre-print
We evaluate our approach on three different serverless applications, where it selects the optimal memory size for 71.7% of the serverless functions and the second-best memory size for 22.3% of the serverless  ...  As our approach does not require dedicated performance tests, it enables cloud providers to implement resource sizing on a platform level and automate the last resource management task associated with  ...  Acknowledgments This work was supported by the AWS Cloud Credits for Research program. The authors would like to thank Alex Casalboni for providing the measurement data behind the motivating examples.  ... 
arXiv:2010.15162v3 fatcat:opzuiwpdhnapfgvn256vk6y22u

Balancing reliability, cost, and performance tradeoffs with FreeFault

Dong Wan Kim, Mattan Erez
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
Because it requires a very modest portion of the cache (as small as 8KB) to cover a large fraction of DRAM faults, FreeFault has almost no impact on performance.  ...  Memory errors have been a major source of system failures and fault rates may rise even further as memory continues to scale.  ...  ACKNOWLEDGMENT The authors acknowledge the Texas Advanced Computing Center for providing HPC resources and the support of the Department of Energy under Award #B599861 and the National Science Foundation  ... 
doi:10.1109/hpca.2015.7056053 dblp:conf/hpca/KimE15 fatcat:mcj3zvmqkrdatdziyvexyof6w4

Bubble-Up

Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
By using a bubble to apply a tunable amount of "pressure" to the memory subsystem on processors in production datacenters, our methodology can predict the performance interference between co-locate applications  ...  Being unable to accurately predict performance degradation due to contention for shared resources on multicore systems has led to the heavy handed approach of simply disallowing the co-location of high-priority  ...  This work was partially supported by Google and NSF grant 0811689 to the University of Virginia.  ... 
doi:10.1145/2155620.2155650 dblp:conf/micro/MarsTHSS11 fatcat:kvjhak47jngglex5hswtwehhcq

A Methodology for Co-Location Aware Application Performance Modeling in Multicore Computing

Daniel Dauwe, Eric Jonardi, Ryan Friese, Sudeep Pasricha, Anthony A. Maciejewski, David A. Bader, Howard Jay Siegel
2015 2015 IEEE International Parallel and Distributed Processing Symposium Workshop  
This study investigates the performance degradation an application experiences from memory interference due to other applications colocated on cores of the same multicore processor.  ...  As multicore processor architectures are now prevalent in server nodes of parallel and distributed computing systems, it has become important to characterize the performance of applications run on these  ...  Our work in [DaF14] measures memory interference from application co-location, and its impact on system performance for a single Intel i7 machine.  ... 
doi:10.1109/ipdpsw.2015.38 dblp:conf/ipps/DauweJFPMBS15 fatcat:xqjtbp6ihvasvprxqdqsiv5vny

Exploring Baseline Concussion Assessment Performance in Adapted Wheelchair Sport Athletes

Ryan N. Moran, Steven P. Broglio, Karla K. Francioni, Jacob J. Sosnoff
2020 Journal of athletic training  
Main Outcome Measure(s) Athletes completed baseline Immediate Post-Concussion Assessment and Cognitive Testing (ImPACT) and the Wheelchair Error Scoring System (WESS) before the start of their respective  ...  Mean errors on the WESS were 3.14 ± 2.9, with 81% committing ≥1 error. Sex differences were not present for symptoms, neurocognitive testing, or balance measures.  ...  at The University of Alabama.  ... 
doi:10.4085/1062-6050-294-19 pmid:32607535 pmcid:PMC7462168 fatcat:bj56kzrq65g73hoz7qwws5ee2a

Archipelago

Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Benjamin G. Zorn
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
We show that Archipelago allows applications to continue to run correctly in the face of thousands of memory errors.  ...  the working set of an application and compacting cold objects.  ...  Acknowledgments The authors would like to thank all of the anonymous reviewers for their careful and detailed reviews.  ... 
doi:10.1145/1346281.1346296 dblp:conf/asplos/LvinNBZ08 fatcat:showzbkrfffz3fp3x3rsypmu2e

Archipelago

Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Benjamin G. Zorn
2008 ACM SIGOPS Operating Systems Review  
We show that Archipelago allows applications to continue to run correctly in the face of thousands of memory errors.  ...  the working set of an application and compacting cold objects.  ...  Acknowledgments The authors would like to thank all of the anonymous reviewers for their careful and detailed reviews.  ... 
doi:10.1145/1353535.1346296 fatcat:yyzn3n2vdrf7nnzcahkgdyrfqi
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