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How to Synchronize a Pausible Clock to a Reference

Robert Najvirt, Andreas Steininger
2015 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems  
: Use ring oscillator referenced with a free running clock The standard pausible clock • Two loops • Timing loop guarantees minimum pulse widths • Switching loop handles pausing and restarting  ...  clock sources • Communicate without risk of metastable upsets Unfortunately impossible • Synchronization impossibility • Pausing and starting a free running clock impossibility Compromise solution  ... 
doi:10.1109/async.2015.10 dblp:conf/async/NajvirtS15 fatcat:xxjcytq5gjfvnhkf7kjbtpwjqu

Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements

Xiaoxiao Wang, Dat Tran, Saji George, LeRoy Winemberg, Nisar Ahmed, Steve Palosh, Allan Dobin, Mohammad Tehranipoor
2012 2012 IEEE International Test Conference  
Furthermore, reliability and FF metastability measurements are performed using the proposed sensor. The measurement results agree with the existing models.  ...  The Radic sensor performs aging, flip-flop (FF) metastability window and variation measurements on-chip. This sensor has been fabricated in a floating gate Freescale SOC in very advanced technology.  ...  A free-running frequency controllable waveform and a reference clock waveform are fed to the data and clock pin of FF under test respectively.  ... 
doi:10.1109/test.2012.6401593 dblp:conf/itc/WangTGWAPDT12 fatcat:onmszz5geza7naajj3jvddj3ma

Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS

Seongjong Kim, Inyong Kwon, D. Fick, Myungbo Kim, Yen-Po Chen, D. Sylvester
2013 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers  
The DFF sampling element has its data pin connected to system clock and its clock pin connected to a free-running ring-oscillator. Two additional DFFs are used to prevent metastability.  ...  Fig. 14.9.3 shows a tunable pulse generator to control clock duty, similar to [3]. Duty cycle is measured with a statistical sampling circuit (Fig. 14.9.3) .  ...  The DFF sampling element has its data pin connected to system clock and its clock pin connected to a free-running ring-oscillator. Two additional DFFs are used to prevent metastability.  ... 
doi:10.1109/isscc.2013.6487728 dblp:conf/isscc/KimKFKCS13 fatcat:lhwpnwsqajdepphqio6ajmf6oi

Synchronizer-Free Digital Link Controller

Johannes Bund, Matthias Fugger, Christoph Lenzen, Moti Medina
2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65nm process running at roughly 2GHz.  ...  The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit.  ...  Additionally we provide lower and upper bounds on the frequency of the clocks which are close to the frequency bounds free-running oscillators of the same quality have.  ... 
doi:10.1109/tcsi.2020.2989552 fatcat:gtnnhj5vgrd5vbijcbaimchrd4

A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction

S. Das, D. Roberts, Seokwoo Lee, S. Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner
2006 2006 IEEE International Conference on IC Design and Technology  
A distributed pipeline recovery mechanism [1] is implemented measurements results of a 64bit processor fabricated in 0. 18ptm to recover correct pipeline state (figure lb).  ...  It achieves of the positive clock phase, when the shadow latch is transparent, 44% energy savings over the worst case operating conditions for a determines the sampling delay of the shadow latch.  ...  An internal clock unit generates Figure 6 shows the distribution of the first failure voltage for the 33 4. Measurement Results measured chips.  ... 
doi:10.1109/icicdt.2006.220829 fatcat:5doezystevgofbap3hpe5hrudm

Portable digital clock generator for digital signal processing applications

T. Olsson, P. Nilsson
2003 Electronics Letters  
A fully integrated clock generator with behaviour similar to a PLL is proposed. A free-running ring oscillator is used as internal clock and the output clock is generated using two counters.  ...  The clock generator is described in synthesisable VHDL-code and can therefore easily be made from standard cells found in any commercial standard CMOS cell library.  ...  To produce such a clock, a simple free-running ring-oscillator can be used. The free-running device consists of a few logic gates and does not consume much power.  ... 
doi:10.1049/el:20030910 fatcat:ypa4vvdffjft7f37z5psgp2wem

A Self-Tuning DVS Processor Using Delay-Error Detection and Correction

S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, T. Mudge
2006 IEEE Journal of Solid-State Circuits  
In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18µm technology .  ...  The metastability detector which shares the dynamic node Err_dyn with the comparator evaluates in the positive phase of the clock when the slave output could become metastable.  ...  The standard positive edge triggered DFF is augmented with a shadow latch which samples at the negative clock edge.  ... 
doi:10.1109/jssc.2006.870912 fatcat:2pe7joh2ubdhtigqu7kkzda3eq

Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip

Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid, Andreas Steininger, Christoph Lenzen
2014 Journal of computer and system sciences (Print)  
We devise self-stabilizing hardware building blocks and a hybrid synchronous/asynchronous state machine enabling metastability-free transitions of the algorithm's states.  ...  We evaluate a prototype implementation, which has been designed in VHDL, using the Petrify tool in conjunction with some extensions, and synthesized for an Altera Cyclone FPGA.  ...  Note that this avoids the need for synchronization with a free-running clock and hence preserves the ASM's continuous time scale.  ... 
doi:10.1016/j.jcss.2014.01.001 pmid:26516290 pmcid:PMC4579925 fatcat:baoxpq3dovcabag3prxwtiq5cy

FPGA Implementation of Metastability-Based True Random Number Generator

Hisashi HATA, Shuichi ICHIKAWA
2012 IEICE transactions on information and systems  
Another type of TRNG exploits the metastability of a latch to generate entropy.  ...  Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.  ...  It should be noted that a Sunar-type TRNG is derived by replacing LUT latches with free-running ring oscillators.  ... 
doi:10.1587/transinf.e95.d.426 fatcat:7hkup7nwrzdfhljerzl7ntvcgy

Detection of metastable electronic states by Penning trap mass spectrometry

R. X. Schüssler, H. Bekker, M. Braß, H. Cakir, J. R. Crespo López-Urrutia, M. Door, P. Filianin, Z. Harman, M. W. Haverkort, W. J. Huang, P. Indelicato, C. H. Keitel (+10 others)
2020 Nature  
We use the high-precision Penning trap mass spectrometer PENTATRAP to measure the cyclotron frequency ratio of the ground state to the metastable state of the ion with a precision of 10-11-an improvement  ...  Here we report the observation of a long-lived metastable electronic state in an HCI by measuring the mass difference between the ground and excited states in rhenium, providing a non-destructive, direct  ...  Ten measurement cycles constitute a measurement run.  ... 
doi:10.1038/s41586-020-2221-0 pmid:32376960 fatcat:gffxztgepzdrhlbvsayn46unse

Mesochronous Clock Based Synchronizer Design for NoC
위상차 클럭 기반 NoC 용 동기회로 설계

Kang-Chul Kim, Jiang Chong
2015 The Journal of the Korea institute of electronic communication sciences  
A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate  ...  This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal.  ...  The mesochronous network is a network in which the clocks run with the same frequency but different phases compared with synchronous network.  ... 
doi:10.13067/jkiecs.2015.10.10.1123 fatcat:p6u5urmn5fgorbm73pfsii3jwm

Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance

Matthias Fugger, Attila Kinali, Christoph Lenzen, Ben Wiederhake
2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This is achieved by using potentially metastable measurement values to delay clock signals while they undergo synchronization, instead of after they are synchronized.  ...  State-ofthe-art solutions incur synchronization delays in the order of several clock cycles to avoid, with sufficient probability, that the clock signal is affected by metastability.  ...  source clock, e.g., an external free-running quartz oscillator.  ... 
doi:10.1109/tcad.2021.3097599 fatcat:djgqfyz7v5fzdn7r2xe444vize

SoC with an integrated DSP and a 2.4-GHz RF transmitter

R.B. Staszewski, R. Staszewski, J.L. Wallberg, T. Jung, Chih-Ming Hung, Jinseok Koh, D. Leipold, K. Maggio, P.T. Balsara
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The use of VHDL allows for a tight and seamless integration of RF with the DSP.  ...  The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space.  ...  . • Low-speed digital (LSD) superblock with clocks running on the retimed reference frequency of 13 MHz. • High-speed digital (HSD) subchip with clocks much faster than the reference frequency; it contains  ... 
doi:10.1109/tvlsi.2005.859587 fatcat:xab3jnstobcb3osbmnwqcwocyi

Midinfrared magneto-optical trap of metastable strontium for an optical lattice clock

R. Hobson, W. Bowden, A. Vianello, I. R. Hill, Patrick Gill
2020 Physical Review A  
in a spin-polarized state to allow high-precision spectroscopy of the 5s^2 ^1S_0 to 5s5p ^3P_0 clock transition.  ...  We report on the realization of a magneto-optical trap (MOT) for metastable strontium operating on the 2.92 μm transition between the energy levels 5s5p ^3P_2 and 5s4d ^3D_3.  ...  Leaving α, s tot , and the overall detuning as free parameters for the fit curve in Figure 5 , we measure a minimum temperature of 5.9(6) µK, corresponding to α = 2.0(1).  ... 
doi:10.1103/physreva.101.013420 fatcat:rdkw7bsxovdv7pmcc7wae2af3a

A jitter characterization system using a component-invariant Vernier delay line

A.H. Chan, G.W. Roberts
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay  ...  Jitter characterization has become significantly more important for systems running at multigigahertz data rates.  ...  However, if the oscillators are free running, noise accumulated within the oscillator will be passed on from one measurement to the next.  ... 
doi:10.1109/tvlsi.2003.820531 fatcat:di2jx4uxtrbyfhehws5j5ornhy
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