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Traffic analysis for on-chip networks design of multimedia applications
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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We believe that our findings open up new directions of research with deep implications on some fundamental issues in on-chip network design for multimedia applications. ...
Using a generic communication architecture, we also discuss the implications of our findings on on-chip buffer space allocation and present quantitative evaluations for typical video streams. ...
This model finds out the lower bound for the probability that the queue length Q exceeds a certain buffer size x, under the assumption of having an infinite buffer. Mathematically: 1. ...
doi:10.1109/dac.2002.1012731
fatcat:tzg4hjzztjbi7ovx2yfxcbdb5a
Traffic analysis for on-chip networks design of multimedia applications
2002
Proceedings - Design Automation Conference
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We believe that our findings open up new directions of research with deep implications on some fundamental issues in on-chip network design for multimedia applications. ...
Using a generic communication architecture, we also discuss the implications of our findings on on-chip buffer space allocation and present quantitative evaluations for typical video streams. ...
This model finds out the lower bound for the probability that the queue length Q exceeds a certain buffer size x, under the assumption of having an infinite buffer. Mathematically: 1. ...
doi:10.1145/513918.514116
dblp:conf/dac/VaratkarM02
fatcat:hetqxprebfcvbfvukv7ivzbehi
Traffic analysis for on-chip networks design of multimedia applications
2002
Proceedings - Design Automation Conference
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A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2006; you can also visit the original URL.
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We believe that our findings open up new directions of research with deep implications on some fundamental issues in on-chip network design for multimedia applications. ...
Using a generic communication architecture, we also discuss the implications of our findings on on-chip buffer space allocation and present quantitative evaluations for typical video streams. ...
This model finds out the lower bound for the probability that the queue length Q exceeds a certain buffer size x, under the assumption of having an infinite buffer. Mathematically: 1. ...
doi:10.1145/514112.514116
fatcat:3b2y7dwrgrbzniv6n5ywuzxfpq
On-chip traffic modeling and synthesis for MPEG-2 video applications
2004
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We believe that our findings open new directions of research with deep implications on some fundamental issues in on-chip networks design for multimedia applications. ...
Index Terms-Communication analysis, long-range dependence, on-chip networks, self-similarity, system-level design. ...
ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their suggestions that improved several drafts of this paper. ...
doi:10.1109/tvlsi.2003.820523
fatcat:yncwhqvvlnd4vnquswynnet7li
Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net
2016
Journal of Integrated Circuits and Systems
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Network-on-Chip (NoC) is a power architecture that emerged to solve communication issues present in modern Systems-on-Chip (SoCs). ...
As results, we have validated and refined the model of a 5×5 mesh NoC comparing its indices with equivalent VHDL RTL description under synthetic and real traffic situations. ...
I INTRODUCTION Network-on-Chip (NoC) is a scalable architecture for on-chip communication that fulfills several requirements of modern Systems-on-Chip (SoCs), such as high communication parallelism and ...
doi:10.29292/jics.v11i2.432
fatcat:aqdg46csbfduxd7suox5i5zqce
Network Calculus Applied to Verification of Memory Access Performance in SoCs
2007
2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia
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SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. ...
The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. ...
We conclude that it is possible to apply network calculus for worst-case analysis of memory access performance in SoCs. ...
doi:10.1109/estmed.2007.4375796
dblp:conf/estimedia/HenrikssonWJB07
fatcat:ha72ylxjnbcnjlrki7v2keaawy
An Analytical Latency Model for Networks-on-Chip
2013
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). ...
It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. ...
We simulate different size networks for 4 flits input and output buffers and 32 flits packets under uniform traffic. ...
doi:10.1109/tvlsi.2011.2178620
fatcat:fi62vugyibbgdi6cwldbxpey7q
Minimising Impact of Local Congestion in Networks-on-Chip Performance by Predicting Buffer Utilisation
2020
2020 31st Irish Signals and Systems Conference (ISSC)
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Networks-on-Chip (NoC) were designed to enhance the communication performance of Multi-processor Systems-on-Chip (MPSoC). ...
NoCs are equipped with buffered input channels which queue incoming data and minimise routing stress especially under uneven traffic distributions. ...
Networks-on-Chip (NoC) was designed to address existing scalability and latency issues. ...
doi:10.1109/issc49989.2020.9180165
fatcat:hl3voqpg7fgvrlkvawzyr4hltm
Computation and communication refinement for multiprocessor SoC design
2006
ACM Transactions on Design Automation of Electronic Systems
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We make such a distinction, for instance, in Section 3.1, where we try to capture the impact of topology on the overall behavior of the network. ...
At the same time, the platform model can emphasize communication (as opposed to computation) aspects where communication volume, packet rates, buffer size, etc., represent the information of interest. ...
Their contribution to bringing many of these ideas to life was essential. ...
doi:10.1145/1142980.1142983
fatcat:mqdulmqw5ngmljor6imi5c3z5i
Performance and cost metrics analysis of a 3D NoC topology using network calculus
2013
Applied Mathematical Sciences
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The packet switching based Network-on-Chip (NoC) is an obvious interconnect design alternative to the shared bus, crossbar or ring based on-chip communication architecture used in System-on-Chips (SoCs ...
In this paper, the traffic related parameters of a 3D NoC topology, namely 3D Recursive Network Topology (3D RNT) are evaluated by using network calculus based methodology and the results of the evaluation ...
Performance and cost metrics analysis
4175
Related works Many topologies and routing algorithms have been developed for 3D Network-on-Chip (3D NoC). ...
doi:10.12988/ams.2013.35281
fatcat:kr236egwinbufox2nnrqwkbuwy
Performance evaluation and design tradeoffs of on-chip interconnect architectures
2011
Simulation modelling practice and theory
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Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. ...
Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. ...
Figure 4 compares the average latency of the three on-chip interconnect architectures under different injection rate using Network Calculus (analysis) and simulation. ...
doi:10.1016/j.simpat.2010.10.008
fatcat:dpwadk5mljdj5nggxtg5oknyce
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
2006
Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06
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Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. ...
We apply the extended method to generate a routing algorithm for a mesh topology network. ...
Delay variation (a) and throughput variation (b) under Transpose 1 traffic.
Figure 5 : 5 Delay variation (a) and throughput variation (b) under traffic generated by a multimedia system. ...
doi:10.1145/1176254.1176289
dblp:conf/codes/PalesiHKC06
fatcat:44z2mqwfyrao7jrc5z3dkvg54y
VLSI Design of A Chip With High Speed Atm Switch-A Review
2021
Turkish Journal of Computer and Mathematics Education
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In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. ...
The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. ...
Yi and Sudeep present a tutorial regarding the possibilities and challenges of photonic network-on-chip as the communication backbone for multicore chips. ...
doi:10.17762/turcomat.v12i2.1451
fatcat:yc5qikn3zrfqrbbtiguegwujnq
Reducing data-memory footprint of multimedia applications by delay redistribution
2007
Proceedings - Design Automation Conference
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It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. ...
We show that this delay redistribution technique can signficantly reduce (up to 70%) the total on-chip memory required. ...
Similar approaches have been followed in the domain of computer networks to counter the burst in network traffic so as to effectively utilize network resources. ...
doi:10.1145/1278480.1278664
dblp:conf/dac/RamanCOD07
fatcat:ve3tey4nvvc53hqrh3wz4qjwr4
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution
2007
Proceedings - Design Automation Conference
Preserved Fulltext
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It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. ...
We show that this delay redistribution technique can signficantly reduce (up to 70%) the total on-chip memory required. ...
Similar approaches have been followed in the domain of computer networks to counter the burst in network traffic so as to effectively utilize network resources. ...
doi:10.1109/dac.2007.375261
fatcat:wiiwqzqylfasnafabpg5eu7o2q
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