2,012 Hits in 9.9 sec

CMOS Control Enabled Single-Type FET NASIC

Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design.  ...  This is enabled by CMOS providing control signals that coordinate the operation of the logic implemented in the nanoscale.  ...  The focus instead is on the new control and circuit scheme and its implications. The fault tolerance techniques as discussed in [1] [2] are directly applicable to the new design style.  ... 
doi:10.1109/isvlsi.2008.92 dblp:conf/isvlsi/NarayananLWM08 fatcat:vve2juhaajfzhl6mycrm2oisfy

CMOS Impulse Radar

Hakon A. Hjortland, Dag T. Wisland, Tor Sverre Lande, Claus Limbodal, Kjetil Meisal
2006 2006 NORCHIP  
As it turns out, the combination of noise, coarse quantization, and also integration, results in systems that, perhaps a bit unexpectedly, have quite good performance.  ...  So-called Suprathreshold Stochastic Resonance (SSR) systems are studied in detail. These systems take a noisy signal as input and then 1-bit quantize it.  ...  ACKNOWLEDGMENT The authors would like to thank the startup company, Novelda AS [14], for their generous support in putting together a working impulse radar system used in our measurements.  ... 
doi:10.1109/norchp.2006.329248 fatcat:o2qc4htubfb5xp553m6avzl7uq

A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

Gongzhi Liu, Lijing Zheng, GuangYi Wang, YiRan Shen, Yan Liang
2019 IEEE Access  
Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor structure are proposed, within which one is based on MRL logic, and the other is an improved one that is implemented by MRL  ...  In several memristor-based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional CMOS technology.  ...  The material implication is considered to be a truth function in logic, and the p IMP q can be expressed as ''p → q'' in a logical expression.  ... 
doi:10.1109/access.2019.2907976 fatcat:lby7ddzzlbbv5jrhd2erxxotcy

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Andras Moritz
2009 Microelectronics Journal  
In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics.  ...  The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology.  ...  Our broader objective is to develop a framework that could be used by research groups in this field and that could help them in their investigation of new materials, devices, and architectures evaluating  ... 
doi:10.1016/j.mejo.2008.07.072 fatcat:te4h6zgiincqfnngggutvziuia

Hybrid CMOS/Memristor Circuit Design Methodology [article]

Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
2021 arXiv   pre-print
RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications.  ...  In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic  ...  A number of 500 programming pulses were used to elicit this kind of response from the device.  ... 
arXiv:2012.02267v2 fatcat:kmltz2x64rdpniuvbzs2lxxdny

Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling [article]

Kaushik Vaidyanathan
2015 arXiv   pre-print
Severe lithography and material limitations seen below the 20 nm node, however, are challenging the fundamental premise of affordable CMOS scaling.  ...  To evaluate the efficacy of the proposed holistic DTCO process, we designed, fabricated and tested several design experiments in a state-of-the-art IBM 14SOI process.  ...  Bitcell Array Boundary and its Implications on Standard Cell Design As conventional geometric shrink of standard cells is not possible below the 32 nm CMOS node, it is essential to DTCO standard cell logic  ... 
arXiv:1509.00885v1 fatcat:5mcetdrz2rbhbbtwwf5av36p2a

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Reinaldo Vega, Takashi Ando, Timothy Philip
2021 IEEE Journal of the Electron Devices Society  
Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement.  ...  In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs.  ...  For instance, one might start with either of measured MFIS NCFET I-V and C-V curves or TCAD-generated curves of the same kind, and then fit a compact model to these curves, and then simulate a RO or logic  ... 
doi:10.1109/jeds.2021.3095923 fatcat:rg3ngha3crhl7n7rbziro4mo3q

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Vinod Kumar Joshi, Prashanth Barla, Somashekara Bhat, Brajesh Kumar Kaushik
2020 IEEE Access  
will have a strong implication.  ...  At the time of writing this article Pu et al. reported the new magnetic logicmemory device by coupling the AHE in magnetic material and insulator-to-metal (ITM) transition in Vanadium dioxide (VO2).  ... 
doi:10.1109/access.2020.3033023 fatcat:jtteh26aw5c6na7whoto2x5d3a

Limitations and challenges of computer-aided design technology for CMOS VLSI

R.E. Bryant, Kwang-Ting Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J.M. Rabaey, A. Sangiovanni-Vincentelli
2001 Proceedings of the IEEE  
While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of  ...  For example, there is a need to design correct and testable chips in a very short time frame and for these chips to meet a competitive requirement.  ...  These two trends are likely to result in a widening gap between the design and manufacturing domains, which will constitute an opportunity for new kinds of design specialization/services.  ... 
doi:10.1109/5.915378 fatcat:jocv62sorfbnjp53u7b76j4mdi

Quantum information density scaling and qubit operation time constraints of CMOS silicon based quantum computer architectures [article]

Davide Rotta, Fabio Sebastiano, Edoardo Charbon, Enrico Prati
2017 arXiv   pre-print
In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it provides the capability of nanometric, serial  ...  By combining the forecast of technology development with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm^2 for  ...  Preliminary studies predict that new materials other than δ QI = 8A QB − Si could be employed as the channel material and 3D integration may become a cheaper alternative to continuing 2D scaling to increment  ... 
arXiv:1704.06365v1 fatcat:qs4645ptfjd3bblnqpgl4wvaqa

Feedback Biasing in Nanoscale CMOS Technologies

T. Singh, T. Saether, T. Ytterdal
2009 IEEE Transactions on Circuits and Systems - II - Express Briefs  
Two different kinds of sensing circuits form the highlight of this thesis.  ...  The circuit, prototyped in a commercial 0.8-m CMOS process, was estimated capable of achieving an accuracy of around 0.2% relative to full-scale which may be sufficient in many applications.  ...  This paper presents the design and measured results of a proof-of-concept prototype implementation of a new interface circuit first proposed in [1].  ... 
doi:10.1109/tcsii.2009.2019162 fatcat:mhylcisaujczjmkcfowonm6wvu

SOI for digital CMOS VLSI: design considerations and advances

Ching-Te Chuang, Pong-Fe Lu, C.J. Anderson
1998 Proceedings of the IEEE  
This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications.  ...  The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed.  ...  In this kind of design, the latches are typically "open" only for a prescribed time to allow the evaluated data to be written into the latches.  ... 
doi:10.1109/5.663545 fatcat:6lcb6y72k5hphoahsmutzgytbi

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Davide Rotta, Fabio Sebastiano, Edoardo Charbon, Enrico Prati
2017 npj Quantum Information  
By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8  ...  Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.  ...  insulator (SOI) devices up to the FinFET geometry adopted in the present 14-nm node. 84 Preliminary studies predict that new materials other than Si could be employed as the channel material and threedimensional  ... 
doi:10.1038/s41534-017-0023-5 fatcat:3mu4euoamfgg7bjyekxqabnmbi

The Challenges of Advanced CMOS Process from 2D to 3D

Henry Radamson, Yanbo Zhang, Xiaobin He, Hushan Cui, Junjie Li, Jinjuan Xiang, Jinbiao Liu, Shihai Gu, Guilei Wang
2017 Applied Sciences  
The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future  ...  Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved.  ...  Conflicts of Interest: The authors declare no conflicts of interest. , 7, 1047  ... 
doi:10.3390/app7101047 fatcat:btsrot53grcd7noefvqfpfsnwa

Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale

Mohammad Hossein Moaiyeri, Ali Jahaniana, Keivan Navia
2011 Nano-Micro Letters  
In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs.  ...  Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs.  ...  In Ref. [7] , the CAD implications of possible new interconnect technologies have been reviewed. Authors of Ref.  ... 
doi:10.1007/bf03353670 fatcat:6sgmurmopjfrdphct6w2hz6qfe
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