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Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking

S. Rahim, B. Rouzeyre, L. Torres, J. Rampon
Eighth IEEE International High-Level Design Validation and Test Workshop  
It is able to achieve matching in presence of complex redundancies, and is able to perform formal equivalence checking in presence of don't cares.  ...  In [5] , matching in the presence of redundant constant input FFs has been addressed and in [11] identification of sequential redundancy is performed.  ...  Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking Solaiman Rahim Bruno Rouzeyre Lionel Torres Jerome Rampon rahim@synplicity.com rouzeyre  ... 
doi:10.1109/hldvt.2003.1252486 dblp:conf/hldvt/RahimRTR03 fatcat:uiltnb3v4bfqpevhexlxq2a7qa

Scalable conditional equivalence checking: An automated invariant-generation based approach

Jason Baumgartner, Hari Mony, Michael Case, Jun Sawada, Karen Yorav
2009 2009 Formal Methods in Computer-Aided Design  
Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades.  ...  However, conditionally equivalent designswithin which internal equivalence may not exist under sequential observability don't care conditions -are notoriously difficult for automated SEC tools.  ...  inactivity or don't care conditions.  ... 
doi:10.1109/fmcad.2009.5351131 dblp:conf/fmcad/BaumgartnerMCSY09 fatcat:abtilmgzqzhplhpcf7pbpjngjy

Recording Synthesis History for Sequential Verification

Alan Mishchenko, Robert Brayton
2008 2008 Formal Methods in Computer-Aided Design  
Experimental results confirm expected substantial savings in runtime of equivalence checking for large designs.  ...  Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimizations are not applied because  ...  The authors are indebted to Jin Zhang for her careful reading and useful suggestions in revising the manuscript.  ... 
doi:10.1109/fmcad.2008.ecp.8 dblp:conf/fmcad/MishchenkoB08 fatcat:imfvcobnajdcdmrmb7oipepfle

Scalable and scalably-verifiable sequential synthesis

Alan Mishchenko, Michael Case, Robert Brayton, Stephen Jang
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
The geometric means for the runtimes for synthesis and sequential verification on this set were 7.8 sec and 4.4 sec, respectively.  ...  This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes.  ...  The authors are indebted to Jin Zhang for her careful reading and useful suggestions in revising the manuscript.  ... 
doi:10.1109/iccad.2008.4681580 dblp:conf/iccad/MishchenkoCBJ08 fatcat:jz6b5og2wvd4ncwar74glbhvom

Logic synthesis in a nutshell [chapter]

Jie-Hong (Roland) Jiang, Srinivas Devadas
2009 Electronic Design Automation  
This chapter covers classic elements of logic synthesis for combinational circuits.  ...  As the name itself suggests, logic synthesis is the process of automatic production of logic components, in particular digital circuits.  ...  Jianwen Zhu of the University of Toronto for valuable feedback on the manuscript.  ... 
doi:10.1016/b978-0-12-374364-0.50013-8 fatcat:zuz2226qfjcgzlgni2vtqc4fnu

Cell-based Logic Optimization [chapter]

Giovanni De Micheli
2000 Architecture Design and Validation Methods  
This chapter surveys techniques for library binding in semicustom technologies.  ...  Emphasis is placed on the algorithmic approach to library binding, with particular reference to covering and matching techniques.  ...  Acknowledgments The Author acknowledges the scienti c contribution of Dr. Luca Benini and Dr. Patrick V uillod in formalizing generalized matching and in applying it to library binding.  ... 
doi:10.1007/978-3-642-57199-2_2 fatcat:334v5kxmavcwrjvs7uwst7oomi

Abstracts of Current Computer Literature

1968 IEEE transactions on computers  
By careful choice of components, use of error-checking circuits, and selected application of redundant hardware, the basic unextended reliability of the VIC is comparable with the state-of-the-art.  ...  These parameters are a generalization of don't care conditions and may be assigned arbitrary values so as to minimize the cost of realizing the functions.  ... 
doi:10.1109/tc.1968.229105 fatcat:2ijvliiwarh2jc2lxnwiyktyjq

1983 Index IEEE Transactions on Computers Vol. C-32

1983 IEEE transactions on computers  
register transfer leveL Pitchumani, Vijay, + , T-CDec 83 1073-1080 redundancy removal; simplification in presence of don't cares.  ...  Logic arrays Asynchronous sequential logic circuits equivalence of arbiter, synchronizer, latch, and inertial delay. Barros, Coding/decoding; cf.  ... 
doi:10.1109/tc.1983.1676190 fatcat:xsogjoynp5dt7mqu6dy4tiodfq

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design

Aijiao Cui, Chip-Hong Chang, Sofiéne Tahar, Amr T. Abdel-Hamid
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
with related watermarking schemes for sequential functions.  ...  Finite state machines (FSMs) are the backbone of sequential circuit design.  ...  First, it judiciously preserves the don't care inputs in the transitions to optimize the design of next state and output decoders.  ... 
doi:10.1109/tcad.2010.2098131 fatcat:ekih7ptabrfabpo5lhxkjdsuum

Sequential Auctions and Externalities [article]

Renato Paes Leme, Vasilis Syrgkanis, Eva Tardos
2011 arXiv   pre-print
We also show that a first price sequential auction for buying or selling a base of a matroid is always efficient, and implements the VCG outcome.  ...  We prove that if sellers hold sequential first price auctions then for unit-demand bidders (matching market) every subgame perfect equilibrium achieves at least half of the optimal social welfare, while  ...  Next we prove the bound of 4 for the mixed case. We focus of a player i and let j = j * (i) denote item assigned to i in the optimal matching.  ... 
arXiv:1108.2452v2 fatcat:5nb2u43gajhe7ew3pkaqikrz4u

Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation

D.W. Bradley, A.M. Tyrrell
2002 IEEE Transactions on Evolutionary Computation  
The human immune system is a remarkable system of interacting cells and organs that protect the body from invasion and maintains reliable operation even in the presence of invading bacteria or viruses.  ...  both complement and create new approaches to the development of fault detection mechanisms for reliable hardware systems.  ...  ACKNOWLEDGMENT The authors would also like to thank the anonymous referees for their helpful and incisive comments.  ... 
doi:10.1109/tevc.2002.1011538 fatcat:uga2vf63qbgvliyjrhf2epzme4

Efficient manipulation of binary data using pattern matching

PER GUSTAFSSON, KONSTANTINOS SAGONAS
2005 Journal of functional programming  
We then show how the pattern matching using this tree automaton can be made adaptive, how redundant tests can be avoided, and how we can further reduce the size of the resulting automaton by taking interferences  ...  Since the size of the tree automaton is exponential in the worst case, we also present an alternative new approach to compiling binary pattern matching which is conservative in space and analyze its complexity  ...  In a binary match, the Value can either be an Erlang term, a bound variable, an unbound variable, or the don't care variable ' '.  ... 
doi:10.1017/s0956796805005745 fatcat:vzqpwltu2fa5pbcfbxch7mdsba

Hierarchical memory management for mutable state

Adrien Guatto, Sam Westrick, Ram Raghunathan, Umut Acar, Matthew Fluet
2018 Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - PPoPP '18  
Perhaps the most important reason for this is their lack of support for efficient in-place updates, i.e., mutation, which is important for the implementation of both parallel algorithms and the run-time  ...  We describe the key algorithms behind our technique, implement them in the MLton Standard ML compiler, and present an empirical evaluation.  ...  Acknowledgments We thank Rohan Yadav for his assistance in the implementation of the benchmarks used in this paper.  ... 
doi:10.1145/3178487.3178494 dblp:conf/ppopp/GuattoWRAF18 fatcat:ixssob3x7bdvnnnj4j2ng2pf2m

Sequential Auctions and Externalities [chapter]

Renato Paes Leme, Vasilis Syrgkanis, Eva Tardos
2012 Proceedings of the Twenty-Third Annual ACM-SIAM Symposium on Discrete Algorithms  
We also show that a first price sequential auction for buying or selling a base of a matroid is always efficient, and implements the VCG outcome.  ...  We prove that if sellers hold sequential first price auctions then for unit-demand bidders (matching market) every subgame perfect equilibrium achieves at least half of the optimal social welfare, while  ...  Next we prove the bound of 4 for the mixed case. We focus of a player i and let j = j * (i) denote item assigned to i in the optimal matching.  ... 
doi:10.1137/1.9781611973099.70 dblp:conf/soda/LemeST12 fatcat:3k2cd2mt4rgzlfdnskzzfd65eu

Model Checking Software Programs with First Order Logic Specifications using AIG Solvers [article]

Fadi A. Zaraket, Mohamad Noureddine
2014 arXiv   pre-print
They are limited to programs of relatively low complexity for the following reasons. (1) A small increase in the bounds can cause a large increase in the size of the translated formula. (2) Boolean satisfiability  ...  1) Sequential circuits are much more succinct than Boolean formulae with no memory elements and preserve the high-level structure of the program. (2) Encoding the problem as a sequential circuit enables  ...  JPF also does not scale well in the presence of loops and branches with long running time.  ... 
arXiv:1409.6825v1 fatcat:3lqtmcsxcjf7rlauyatk5s3g6y
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