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A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing

Chenxin Zhang, Liang Liu, Dejan Markovic, Viktor Owall
2015 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 mm 2 core area and is capable of running at 500 MHz.  ...  Compared to state-of-theart designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs  ...  of total operations mapped onto the vector core for exploiting extensive DLP and attaining high resource sharing.  ... 
doi:10.1109/tcsi.2014.2366812 fatcat:pblgjc7rcbfxxpgc5z4lghnd5m

Energy-Efficient Software-Defined Radio Solutions For Mimo-Based Broadband Communication

Bruno Bougard, Andre Bourdoux, Frederik Naessens, Miguel Glassee, Veerle Derudder, Liesbet Van der Perre
2007 Zenodo  
Publication in the conference proceedings of EUSIPCO, Poznan, Poland, 2007  ...  Moreover, it mostly relies on a limited set of well-known algorithms (Viterbi, RS, turbo, belief-propagation). Therefore, configurable application specific VLSI architectures are usually considered.  ...  The first part of the flow yields sequential code that still has to be assigned, scheduled and mapped on the platform cores. The AGC thread is assigned to the DFE tile controller.  ... 
doi:10.5281/zenodo.40436 fatcat:gxvopbtfvnd53lvetqt23vr62m

Prototyping For Mimo Systems - An Overview

Thomas Kaiser, Andreas Wilzeck, Martin Berentsen, M. Rupp
2004 Zenodo  
Publication in the conference proceedings of EUSIPCO, Viena, Austria, 2004  ...  Of particular relevance for meaningful applications of MIMO technology is the behaviour of algorithms in a multi-user scenario.  ...  ), some supporting mixtures of DSPs and FPGAs, a general method for mapping the signal processing algorithms onto such platform is not available.  ... 
doi:10.5281/zenodo.38478 fatcat:b3y2rphl5ffafonrsvrj6svl6u

A parallel hybrid merge-select sorting scheme for K-best LSD MIMO decoder on a dynamically reconfigurable processor

Zong Wang, Ahmet T. Erdogan, Tughrul Arslan
2010 21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications  
Several popular sorting algorithms adopted in MIMO decoding are analyzed and mapped onto our proposed platform.  ...  In this paper, we propose a parallel hybrid merge-select sorting approach for the implementation of K-best list sphere detection (LSD) multi-input multi-output (MIMO) decoder based on a recently developed  ...  Several popular sorting algorithms adopted in MIMO decoding were analyzed and mapped onto our proposed platform.  ... 
doi:10.1109/pimrc.2010.5671769 dblp:conf/pimrc/WangEA10 fatcat:65kgicjigzeojghkhceyom7m6e

A Survey Of Baseband Architecture For Software Defined Radio

M. A. Fodha, H. Benfradj, A. Ghazel
2016 Zenodo  
This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed.  ...  The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints.  ...  BP-ASP [22] is a Baseband Processing Application Specific Processor based on Open Air Interface Express MIMO platform [23] .  ... 
doi:10.5281/zenodo.1126159 fatcat:mdhjmvmfafdarg7m6uezpuxiei

System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station

Tang Shan, Zhu Ziyuan, Su Yongtao
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
To meet performance requirements and special constraints on the cost and size, we design a heterogeneous multi-processor SoC for small cell base station, which is composed of ASP (Application Specific  ...  Finally, the results of silicon implementation on SMIC 55nm technology are presented. Index Terms-System-level design, MP-SoC, ASP-algorithm joint optimization, multi-core architecture exploration  ...  After creation of the task graph, it can be mapped onto the virtual hardware platform model shown in the lower part of Fig. 6 .  ... 
doi:10.7873/date.2014.211 dblp:conf/date/TangZS14 fatcat:tynq7fxfafhi3oeakjhmospdjy

Sphere Decoding for Multiprocessor Architectures

Q. Qi, C. Chakrabarti
2007 Signal Processing Systems Design and Implementation (siPS), IEEE Workshop on  
The PDSD algorithm is designed for efficient implementation on programmable multi-processor platforms.  ...  to specific SNR conditions.  ...  In this study, we validated the theoretical performance of PDSD. In the next phase, we will investigate issues in the actual implementation of PDSD on a specific multi-core processor platform.  ... 
doi:10.1109/sips.2007.4387516 dblp:conf/sips/QiC07 fatcat:ktbato4qh5hupacloirhnlp7vm

FPGA-Based Soft-Core Processors for Image Processing Applications

Moslem Amiri, Fahad Manzoor Siddiqui, Colm Kelly, Roger Woods, Karen Rafferty, Burak Bardak
2016 Journal of Signal Processing Systems  
The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA  ...  An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification  ...  Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http:// creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution  ... 
doi:10.1007/s11265-016-1185-7 pmid:32226579 pmcid:PMC7089673 fatcat:5oenzxqh4natzdxpai2u6gyntu

Simulating The Long Term Evolution Physical Layer

Dagmar Bosanska, Josep Colom Ikuno, Christian Mehlführer, M. Rupp, Martin Wrulich
2009 Zenodo  
Publication in the conference proceedings of EUSIPCO, Glasgow, Scotland, 2009  ...  This work has been funded by mobilkom austria AG, the Christian Doppler Laboratory for Wireless Technologies for Sustainable Mobility, as well as the Institute of Communications and Radio-frequency Engineering  ...  The standard only defines the messages exchanged between the base-stations while the algorithms and the exact implementation of the interference mitigation remain vendor specific and are currently a hot  ... 
doi:10.5281/zenodo.41305 fatcat:zms5tylakzgqjf2ij6taitrid4

MAPS: A Software Development Environment for Embedded Multicore Applications [chapter]

Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jeronimo Castrillon, Weihua Sheng
2017 Handbook of Hardware/Software Codesign  
This chapter closes by discussing early experiences of transferring the MAPS technology into Silexica GmbH, a start-up company that provides multi-core programming tools.  ...  To enable the full potential of these platforms, new tools are needed to tackle the programming complexity of MPSoCs, while allowing for high productivity.  ...  multi-core DSP platform.  ... 
doi:10.1007/978-94-017-7267-9_2 fatcat:edvpch6zmjbo5fbzkymd2eblnm

Using Graphics Processing Units in an LTE Base Station

Qi Zheng, Yajing Chen, Hyunseok Lee, Ronald Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott Mahlke, Trevor Mudge
2014 Journal of Signal Processing Systems  
We also study the mapping method of key kernels onto a multi-GPU system to minimize the number of required GPUs and the overall subframe processing latency.  ...  In this work, we develop parallel implementations of key kernels to evaluate the merits of using GPUs as the baseband signal processor.  ...  We explore a multi-GPU configuration for high data rate applications, and study different mapping methods of key kernels onto a multi-GPU system when considering the LTE throughput constraint and the inter-GPU  ... 
doi:10.1007/s11265-014-0932-x fatcat:q6sxgnnygrcehhfdeizgkl7jiy

Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors

Julien Heulot, Jani Boutellier, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi
2013 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013)  
As the number of cores increases in new DSP platform designs, scheduling of applications is becoming a complex operation.  ...  Meanwhile, the variability of the scheduled applications also tends to increase as applications become more sophisticated. Such variations require runtime adaptivity of application scheduling.  ...  Although the use of multi-core processors is widespread, the system-level complexity of the platforms causes myriad problems which still remain unsolved.  ... 
doi:10.1109/ahs.2013.6604235 dblp:conf/ahs/HeulotBPNA13 fatcat:ckximgmphvf7zafaggd7vdp3ze

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications.  ...  Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption.  ...  Performance results The LTE modem application is mapped onto all three different platforms from heterogeneous to fully homogeneous.  ... 
doi:10.1109/date.2010.5457213 dblp:conf/date/JalierLJSBT10 fatcat:654uvmrdsjh6regnjrdiwon32a

Implementation of a High Throughput Soft MIMO Detector on GPU

Michael Wu, Yang Sun, Siddharth Gupta, Joseph R. Cavallaro
2010 Journal of Signal Processing Systems  
Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver.  ...  We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGAlike performance and handle different configurations in software on GPU.  ...  Specifically, each thread block is mapped onto an SM. During execution, the kernel divides the threads into groups of 32.  ... 
doi:10.1007/s11265-010-0523-4 fatcat:2np5q6eehjaulb7zoal4n7x34y

System-Level Characterization Of A Real-Time 4X4 Mimo-Ofdm Transceiver On Fpga

Simon Haene, David Perels, Wolfgang Fichtner
2007 Zenodo  
Publication in the conference proceedings of EUSIPCO, Poznan, Poland, 2007  ...  The equalization of spatial streams, instead, is specific to MIMO receivers and requires about 30% of the FPGA slices and 50% of the multipliers with linear MMSE detection.  ...  FPGA Implementation Results The entire digital signal processing (as shown in Fig. 2 ) is running on a single XC2V6000-6 FPGA, with the exception of DUC, DDC, and digital AGC, which are mapped onto two  ... 
doi:10.5281/zenodo.40437 fatcat:k4psonq2rjcfxekvsdvpv3raxi
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